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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date Jul 1996

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Displaying Results 1 - 12 of 12
  • Process compilation of thin film microdevices

    Publication Year: 1996 , Page(s): 745 - 764
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1828 KB)  

    This paper describes a systematic method for the automatic generation of fabrication processes of thin film devices. The method uses a partially ordered set (poset) representation of device topology describing the order between its various components in the form of a directed acyclic graph. The sequence in which these components are fabricated is determined from the poset linear extensions, and the component sequence is expanded into a corresponding process flow. The graph-theoretic synthesis method is powerful enough to establish existence and multiplicity of flows thus creating a design space D suitable for optimization. The cardinality ||D|| for a device with N components is large with a worst case ||D||⩽(N-1)! yielding in general a combinatorial explosion of solutions. The number of solutions is controlled through a priori estimates of ||D|| and condensation of the device graph. The method has been implemented in the computer program MISTIC (Michigan Synthesis Tools for Integrated Circuits) which calculates specific process parameters using an internal database of process modules and materials. Currently, MISTIC includes process modules for deposition, lithography, etching, ion implantation, coupled simultaneous diffusions, and reactive growth. The compilation procedure was applied to several device structures. For a double metal twin-well BiCMOS structure, the compiler generated 168 complete process flows View full abstract»

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  • Valid clock frequencies and their computation in wavepipelined circuits

    Publication Year: 1996 , Page(s): 791 - 807
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1364 KB)  

    It is known that wavepipelined circuits offer high performance, because their maximum clock frequencies are limited only by the path delay differences of the circuits, as opposed to the longest path delays. For proper operation, precision in clock frequency is essential. Using a new representation, Timed Boolean Functions, we derive analytical expressions for valid clocking intervals in terms of topological, 2-vector, and single vector delays, both the longest and the shortest. These intervals take into account both circuit functionality and timing characteristics, thus eliminating the pessimism caused by long and short false paths, and include effects of circuit parameters such as delay variations, clock skews, and setup and hold times of flip flops. In addition, we show that these intervals subsume Cotten's lower bound on valid clock period. Further, we study the problem of computing all enact valid clocking intervals and its computational complexity by demonstrating discontinuity and nonmonotonicity of the harmonic number H(τ) (the number of valid simultaneous data waves allowed) as a function of the clock period τ. Finally, we propose algorithms to compute the exact valid intervals for a given set of harmonic numbers and demonstrate performance enhancement of balanced circuits from ISCAS benchmarks with gate delay variations View full abstract»

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  • A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities

    Publication Year: 1996 , Page(s): 775 - 790
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1224 KB)  

    Frequency domain analysis of switched-capacitor and other clocked circuits including nonlinearities is a difficult problem requiring special attention. Conventional nonlinear frequency response methods are computationally intensive and time consuming for circuits with large transient components. In this paper, we present a novel technique for the rapid estimation of the nonlinear frequency response of switched-capacitor circuits. The analysis technique is formulated using a multifrequency sinusoidal excitation to drive the circuit into its steady-state condition. Then, the fundamental components are extracted using a frequency-directed Discrete Fourier Transform (DFT) in order to construct the frequency response. The key steps of this approach include the selection of noninterfering input frequencies and the determination of properly scaled input amplitudes. In addition, a method is proposed to reach steady-state quickly and to detect the steady-state condition for use in conjunction with the multifrequency approach described here View full abstract»

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  • EARTH: combined state assignment of PLA-based FSM's targeting area and testability

    Publication Year: 1996 , Page(s): 727 - 731
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    Stuck-at and crosspoint faults in PLA's introduce combinational and sequential redundancies in PLA-based FSM's that affect the testability of these FSM's. We propose a new state assignment algorithm for PLA-based FSM's called EARTH that simultaneously considers area minimization and testability of the resultant PLA's. Our fault model is the single stuck-at and/or single crosspoint fault model. Experimental results show that, on an average, the number of undetectable faults which result due to state assignment by EARTH is about five times less than those generated due to state assignment by NOVA with area overhead 2% more than NOVA View full abstract»

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  • FASY: a fuzzy-logic based tool for analog synthesis

    Publication Year: 1996 , Page(s): 705 - 715
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy-logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two-phase optimizer sizes all elements to satisfy the performance constraints minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies View full abstract»

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  • Accelerated waveform methods for parallel transient simulation of semiconductor devices

    Publication Year: 1996 , Page(s): 716 - 726
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB)  

    Simulating transients in semiconductor devices involves numerically solving the time-dependent drift-diffusion equations, usually in two or three space dimensions. Because of the computation cost of these simulations, methods that perform careful domain decomposition so as to exploit parallel processing have received much recent attention. In this paper, we describe using accelerated waveform relaxation (WR) to perform parallel device transient simulation using both clusters of workstations and the IBM SP-2. The accelerated WR algorithms are compared to pointwise direct and iterative methods, and it is shown that the accelerated WR method is competitive on a single processor. In addition, it is shown that with a domain decomposition chosen for rapid iterative method convergence rather than parallel efficiency, the pointwise methods parallelize poorly but the WR method achieves near linear speedup (with respect to the number of processors) on the IBM SP-2 View full abstract»

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  • Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

    Publication Year: 1996 , Page(s): 765 - 774
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1616 KB)  

    In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigated View full abstract»

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  • Functional test generation for synchronous sequential circuits

    Publication Year: 1996 , Page(s): 831 - 843
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1224 KB)  

    We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLAs are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator. Results on a broad class of small to large synthesis benchmark PSM's from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS'89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests View full abstract»

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  • Pseudorandom test-length analysis using differential solutions

    Publication Year: 1996 , Page(s): 815 - 825
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB)  

    As the size of VLSI circuits increases, the use of random testing is becoming more common. One of the most important aspects of random testing is the determination of the test pattern length that guarantees a high confidence of fault detection. Generally, random test length is estimated by assuming that the set of test patterns applied is purely random. The assumption is not completely correct in applications where linear feedback shift registers (LFSR's) are employed to generate input vectors. In this paper, we have developed a test (Markov) model which faithfully reflects the pseudorandom behavior of test patterns, and all detectable single stuck-at faults (instead of the worst single stuck-fault only) are considered. The required test length is then determined by solving differential equations to achieve the specified test confidence. Based on the test model, analysis is first dedicated to the two-fault case, results are then extended to the k-fault analysis where k⩾3. The test length thus determined is smaller than that derived based on the random pattern assumption, and test costs can be greatly reduced View full abstract»

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  • Analysis of convergence properties of a stochastic evolution algorithm

    Publication Year: 1996 , Page(s): 826 - 831
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    In this paper, the convergence properties of a stochastic optimization algorithm called the stochastic evolution (SE) algorithm is analyzed. We show that a generic formulation of the SE algorithm can be modeled by an ergodic Markov chain. As such, the global convergence of the SE algorithm is established as the state transition from any initial state to the globally optimal states. We propose a new criterion called the mean first visit time (MFVT) to characterize the convergence rate of the SE algorithm. With MFVT, we are able to show analytically that on average, the SE algorithm converges faster than the random search method to the globally optimal states. This result Is further confirmed using the Monte Carlo simulation View full abstract»

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  • Modeling and simulation of broken connections in CMOS IC's

    Publication Year: 1996 , Page(s): 808 - 814
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    This paper presents a fault model, called node-break fault model, to effectively account for broken connections inside CMOS circuits. The proposed model is very general since it allows to generate test vectors for broken connections that cannot be detected by means of test sequences for stuck-open faults. In addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node, thus superseding the stuck-open fault model. The model can be used to derive tests and to perform fault simulations independent of the actual layout of the circuit. Conditions for the detection of broken connections are derived from electrical considerations (aimed at verifying the presence of electrical continuity between the terminals of transistors connected to a node) while the minimum number of input vectors to test for broken connections in a node is determined by graph theory. Fault simulations performed on benchmark circuits using test sequences oriented to the detection of stuck-open faults show their inadequacy in detecting node-break faults, thus claiming for considering such a fault model in the test pattern generation View full abstract»

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  • Permissible functions for multioutput components in combinational logic optimization

    Publication Year: 1996 , Page(s): 732 - 744
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1404 KB)  

    This paper is concerned with logic optimization of multilevel combinational logic circuits. In the light of theoretical work of the past years, where a circuit is modeled by a Boolean network in which each node implements a single-output Boolean function, we address how a concurrent optimization over multiple nodes or components can lead to further optimization compared to conventional minimization techniques. In particular, we provide a procedure for computing maximally compatible sets of permissible relations for multiple nodes. This is a generalization of the classical notion of a compatible set of permissible functions for a single node, where no method is known for correctly computing such a maximal set. We provide a method for computing the set correctly for the general case. Based on this, we develop and implement a procedure for optimizing multiple nodes concurrently. The proposed procedure has been implemented, and we present experimental results View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu