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Solid-State Circuits, IEEE Journal of

Issue 6 • Date Jun 1996

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Displaying Results 1 - 17 of 17
  • A programmable FIR digital filter using CSD coefficients

    Page(s): 869 - 874
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology View full abstract»

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  • A 2×2 analog memory implemented with a special layout injector

    Page(s): 856 - 859
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    Using floating gate MOSFETs, we have designed a 2×2 analog memory, which is expandable to any size array. The reduced programming voltage due to the innovative floating gate MOSFETs enables us to construct the analog memory with a standard double poly n-well process. In addition, a novel programming algorithm is presented. This method will contribute not only to a reduced total programming time, but also to a prolonged lifetime of the memory. The high voltage program/erase pulses are arranged to minimize the disturbance of nonselected cells. The resolution of a memory cell has been found to be 10 mV over a range of 1.25 V to 2 V which is equivalent to the information content of 6 digital cells View full abstract»

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  • A 1.2 GFLOPS neural network chip for high-speed neural network servers

    Page(s): 860 - 864
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    This paper describes a digital neural network chip for high-speed neural network servers. The chip employs single-instruction multiple-data stream (SIMD) architecture consisting of 12 floating-point processing units, a control unit, and a nonlinear function unit. At a 50 MHz clock frequency, the chip achieves a peak speed performance of 1.2 GFLOPS using 24-bit floating-point representation. Two schemes of expanding the network size enable neural tasks requiring over 1 million synapses to be executed. The average speed performances of typical neural network models are also discussed View full abstract»

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  • A 64-bit carry look ahead adder using pass transistor BiCMOS gates

    Page(s): 810 - 818
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1132 KB)  

    This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder View full abstract»

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  • A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications

    Page(s): 804 - 809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    Swing restored pass-transistor logic (SRPL), a high-speed, low-power logic circuit technique for VLSI applications, is described. By the use of a pass-transistor network to perform logic evaluation and a latch-type swing restoring circuit to drive gate outputs, this technique renders highly competitive circuit performance. An SRPL based multiply and accumulate circuit for multimedia applications is implemented in double metal 0.4 μm CMOS technology View full abstract»

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  • A theoretical design basis for minimizing CMOS fixed taper buffer area

    Page(s): 865 - 868
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    This paper develops a theoretical basis for the minimization of chip area required for fixed taper buffer design. It modifies the well-known procedure for minimizing delay time in such circuits to derive a minimum number of required stages. Rather than minimize delay time, the procedure realizes a specified buffer delay time using a stage-area scale factor that minimizes the total area of the buffer. Since an integer number of tapered stages must be used while the calculations lead to noninteger results, the effects of roundoff errors are included View full abstract»

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  • A full bit prefetch DRAM sensing circuit

    Page(s): 767 - 772
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    A DRAM sensing circuit that achieves both a fast RAS access time and a high-bandwidth burst operation is proposed. For the data burst capability of synchronous DRAM's, 256-bit-long data I/O lines are divided into eight segments. A small local latch is provided for each segment of 32 bit-line pairs to prefetch eight data out of the 256 sense amplifiers. A local buffer is connected to eight local latches through selection switches. Burst read operations, up to eight bits, are done by activating selection switches and the local buffer serially. Besides this prefetch capability, the segmented data I/O line results in very small capacitance, only 0.09 pF. The sensing scheme uses nMOS bit switches and a full Vdd precharge voltage for bit and segmented data I/O lines. Then, after sense amplifiers are turned on, only low-going bit lines are connected to the segmented data I/O lines without any voltage disturbance because of the small capacitance. The proposed circuit, therefore, realizes a high-speed RAS access, which is 16 ns faster than a conventional DRAM. A circuit layout design based on a 0.5-μm design rule shows no area impact View full abstract»

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  • A GHz MOS adaptive pipeline technique using MOS current-mode logic

    Page(s): 784 - 791
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    This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-μm MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits View full abstract»

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  • An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

    Page(s): 773 - 783
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB)  

    A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54×54-bit multiplier is designed with this architecture. It is fabricated by 0.5 μm CMOS with triple level metal technology. The active area size is 3.0×3.08 mm2 and the number of transistors is 78,800. This is the smallest number for all 54×54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54×54-bit multipliers with 0.5-μm CMOS View full abstract»

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  • A 1.3-ns 32-word×32-bit three-port BiCMOS register file

    Page(s): 758 - 766
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB)  

    This paper describes a CMOS multiport static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word×32 bit three-port register file has been designed and implemented using this cell. The register file was fabricated in a 0.6-μm BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20°C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz View full abstract»

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  • Large bandwidth BiCMOS operational amplifiers for SC video applications

    Page(s): 828 - 834
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    A single-ended and a fully differential broadband BiCMOS operational amplifier for switched-capacitor video applications are presented. The amplifiers feature a folded cascode gain stage with a current source as output load. For the single-ended amplifier the current mirroring is accomplished with a modified bipolar Wilson current mirror at the output of the differential pair. Symbolic expressions for the transfer functions for both amplifiers are derived. The amplifiers are integrated in an analog 1 μm BiCMOS process with an active die area of 0.72 mm2 and 0.96 mm2 for the single-ended and the fully differential amplifier, respectively. For both amplifiers a DC-gain of 68 dB and a unity gain frequency greater than 250 MHz was measured for a power supply voltage of 5 V View full abstract»

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  • A tunable pulse-shaping filter for use in a nuclear spectrometer system

    Page(s): 850 - 855
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    A pulse-shaping filter for use in a nuclear spectrometer system is described. The filter is designed using tunable gm blocks in order to allow for an adjustable peaking time. Fully differential structures are employed to achieve sufficient pulse height linearity View full abstract»

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  • A GaAs MMIC chip-set for mobile communications using on-chip ferroelectric capacitors

    Page(s): 835 - 840
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    A GaAs MMIC chip-set applicable for various mobile communication systems has been developed. The chip-set consists of (1) low-noise amplifier (LNA) with diversity switching capability and (2) integrated mixer with an amplifier for local oscillator signal. The notable feature of these ICs is the dramatic reduction of pin counts and the improvement of high frequency characteristics due to on-chip ferroelectric bypass capacitors of barium strontium titanium (εr=300). These ICs can be mounted in a small mini-mold package with 6-pin counts View full abstract»

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  • Top-down pass-transistor logic design

    Page(s): 792 - 803
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1380 KB)  

    The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called “circuit inventor” is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed View full abstract»

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  • Performance of CMOS differential circuits

    Page(s): 841 - 846
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    Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique View full abstract»

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  • Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

    Page(s): 819 - 827
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and CL=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied View full abstract»

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  • A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier

    Page(s): 847 - 849
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    A feedforward technique using frequency-dependent current mirrors for a low-voltage wideband amplifier is presented. In the conventional single-stage wideband amplifiers, the folded cascode structure is used. However, the common-gate transistor requires an additional VDS sat and reduces the available output voltage range. In this study the cascode structure is avoided; instead, a frequency-dependent current mirror, whose input impedance becomes higher for a higher frequency, is used to form the feedforward path from the input of the current mirror with a feedforward capacitor. This technique is effective to improve a 100 MHz-1 GHz frequency characteristic of the amplifier. The amplifier has been fabricated using the standard 0.8 μm CMOS process. The phase margin is improved from 46-66° without sacrificing the unity gain frequency of 133 MHz compared with the amplifier without this technique. The amplifier operates at 2.5 V power supply voltage and consumes 12 mW View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan