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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 2 • Date June 1996

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Displaying Results 1 - 15 of 15
  • High-level library mapping for arithmetic components

    Publication Year: 1996, Page(s):157 - 169
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1391 KB)

    We describe high-level library mapping (HLLM), a technique that permits reuse of complex RT-level databook components (specifically ALUs). HLLM can be used to couple existing databook libraries, module generators and custom-designed components with the output of architectural or behavioral synthesis. In this paper, we define the problem of high-level library mapping, present some algorithmic formu... View full abstract»

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  • A new algorithm for implementation of design functions by available devices

    Publication Year: 1996, Page(s):170 - 180
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1235 KB)

    In CAD systems, it is often required to implement desired behaviors by some available device. The selection of the device that can implement the behavior, and the required interfacing, is usually done by human experts. The interface consists of transformations that may have to be performed on the inputs and outputs of the device. This paper describes an approach to automatically derive the specifi... View full abstract»

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  • Component selection for high-performance pipelines

    Publication Year: 1996, Page(s):181 - 194
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1624 KB)

    The use of a realistic component library with multiple implementations of operators results in cost-efficient designs; slow components can then be used on noncritical paths and the more expensive components on only the critical paths. This paper presents a cost-optimized algorithm for selecting components and pipelining a data-flow graph, given such a library, and throughput and latency constraint... View full abstract»

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  • A real-time clustering microchip neural engine

    Publication Year: 1996, Page(s):195 - 209
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2341 KB)

    This paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm, but has been modified resulting in a more VLSI-friendly algorithm that allows a more efficient hardware implementation with simple circuit operators, little memory requirements, modular chip assembly capability, and higher speed fi... View full abstract»

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  • Planar clock routing for high performance chip and package co-design

    Publication Year: 1996, Page(s):210 - 226
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1512 KB)

    A new concept of chip and package co-design for the clock network is presented in this paper. We propose a two level clock distribution scheme which partitions the clock network into two levels. First, the clock terminals are partitioned into a set of clusters. For each cluster, a local on-chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside thi... View full abstract»

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  • On the effectiveness of residue code checking for parallel two's complement multipliers

    Publication Year: 1996, Page(s):227 - 239
    Cited by:  Papers (12)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1514 KB)

    The effectiveness of residue code checking for online error detection in parallel two's complement multipliers has only up until now been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for comp... View full abstract»

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  • A general framework for vertex orderings with applications to circuit clustering

    Publication Year: 1996, Page(s):240 - 246
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    Vertex orderings have been successfully applied to problems in netlist clustering and for system partitioning and layout. We present a vertex ordering construction that encompasses most reasonable graph traversals. Two parameters-an attraction function and a window-provide the means for achieving various graph traversals and addressing particular clustering requirements. We then use dynamic progra... View full abstract»

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  • Four-phase micropipeline latch control circuits

    Publication Year: 1996, Page(s):247 - 253
    Cited by:  Papers (108)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (737 KB)

    Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are level sensitive, so two- to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful i... View full abstract»

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  • Synthesis of initializable asynchronous circuits

    Publication Year: 1996, Page(s):254 - 263
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1181 KB)

    We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper con... View full abstract»

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  • Design of minimal-level PLA self-testing checkers for m-out-of-n codes

    Publication Year: 1996, Page(s):264 - 272
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1117 KB)

    This paper presents the design of minimal-level PLA self-testing checkers (STCs) for incomplete m-out-of-n (m/n) codes and 1-out-of-n (1/n) codes. All checkers are selftesting for three classes of typical PLA faults and hence they are all crosspoint irredundant. A number of various incomplete m/n codes which exhibit the two-closure property with balanced partitioning are constructed, which allow o... View full abstract»

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  • Computing lower bounds on functional units before scheduling

    Publication Year: 1996, Page(s):273 - 279
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    The authors present a new polynomial-time algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds that can be found by relaxing either the precedence constraints or integrality constraints on the sche... View full abstract»

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  • Automatic synthesis of dynamically configured pipelines supporting variable data initiation intervals

    Publication Year: 1996, Page(s):279 - 285
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (731 KB)

    The authors propose a new approach for synthesizing the dynamically configured pipelines supporting variable data initiation intervals (DIIs). Compared to the previous research where the pipeline synthesis is confined to those with fixed DIIs, the proposed system allows powerful design space exploration by removing the constraints of fixed DIIs. The proposed algorithm tries to optimize the area of... View full abstract»

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  • Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

    Publication Year: 1996, Page(s):286 - 291
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (833 KB)

    An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the ... View full abstract»

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  • Self-timed divider based on RSD number system

    Publication Year: 1996, Page(s):292 - 295
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The authors propose a divider structure that combines a novel self timed ring structure and a carry-propagation-free division algorithm. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, an even better performance can be achieved. The authors... View full abstract»

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  • FIRE: a fault-independent combinational redundancy identification algorithm

    Publication Year: 1996, Page(s):295 - 301
    Cited by:  Papers (55)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    FIRE is a novel Fault-Independent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtracking-based exhaustive search performed by fault-oriented automatic test generation algorithms, and identifies redundant... View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu