By Topic

Electron Devices, IEEE Transactions on

Issue 6 • Date Jun 1996

Filter Results

Displaying Results 1 - 25 of 31
  • Hysteresis behavior in 85-nm channel length vertical n-MOSFETs grown by MBE

    Publication Year: 1996 , Page(s): 973 - 976
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages VDS>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Responsivity and impact ionization coefficients of Si1-xGex photodiodes

    Publication Year: 1996 , Page(s): 977 - 981
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    The spectral response and impact ionization coefficient ratio of Si1-xGex have been determined. Measurements were made on p+-i-n+ diodes grown by solid/gas source molecular beam epitaxy. The diodes are characterized by reverse breakdown voltages of 4-12 V and dark currents of 20-170 pA/μm2 . The long wavelength cut-off of the diodes increases from 1.2 μm to 1.6 μm as x increases from 0.08 to 1.0 with a maximum responsivity of 0.5 A/W in all the diodes tested. The ratio α/β varies from 3.3 to 0.3 in the same composition range, with α/β=1 at x≅0.45. These results have important implications in the use of this material system in various photodetection applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thickness dependence of boron penetration through O2 and N2O-grown gate oxides and its impact on threshold voltage variation

    Publication Year: 1996 , Page(s): 982 - 990
    Cited by:  Papers (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    We report on a quantitative study of boron penetration from p+ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O2 or N2O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, NB, for thicknesses other than those measured. We find that the minimum tox required to inhibit boron penetration is always 2-4 nm less when N2O-grown gate oxides are used in place of O2- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on tox, incremental variations in oxide thickness result in a large variation in NB , leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 1011 cm-2 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Enhanced CAD model for gate leakage current in heterostructure field effect transistors

    Publication Year: 1996 , Page(s): 845 - 851
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFETs) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFETs fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FETs, i.e., GaAs MESFETs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Observation of single interface traps in submicron MOSFET's by charge pumping

    Publication Year: 1996 , Page(s): 940 - 945
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    The observation of single interface traps in small area MOSFET's by charge pumping is demonstrated for the first time, The dependence of the single trap charge pumping current on the base level voltage is described, Also the creation of one single interface trap under influence of low level hot carrier injection is demonstrated. A prediction of the charge pumping current behavior as a function of rise and fall time and temperature for the case of individual traps is made. The correlation with RTS-noise experiments is discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Deep submicron CMOS based on silicon germanium technology

    Publication Year: 1996 , Page(s): 911 - 918
    Cited by:  Papers (40)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 μm. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si/SiO2 interface scattering by the inclusion of a capping layer, results in significant velocity overshoot close to the source-end of the channel. The cut-off frequency, ft , is found to increase by around 50% for n-channel devices while more than doubling for p-channel devices for typical estimates of mobility. The results offer the prospect of a more balanced CMOS and improved circuit speed especially when using dynamic logic View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling noise correlation behavior in dual-collector magnetotransistors using small signal equivalent circuit analysis

    Publication Year: 1996 , Page(s): 883 - 888
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    We present a distributed small signal equivalent circuit model based on hybrid-π for modeling of the low-frequency noise correlation behavior in dual-collector magnetotransistors (MTs). The model is based on the assumption that the noise sources at the emitter-base junction of the transistor are spatially correlated; the degree of spatial correlation in noise sources being limited by the intrinsic base spreading resistance. This gives rise to a degradation in correlation of terminal collector noise currents at high current, or injection, levels due to nonuniformities in the dc bias current distribution View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of an efficient, low voltage, third harmonic, large-orbit gyrotron amplifier with a vane-resonator output cavity

    Publication Year: 1996 , Page(s): 1021 - 1028
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    We present the design of a 100 kW, J-band, third harmonic large-orbit gyrotron amplifier which utilizes the interaction between a 45 kV, 4 A beam and a vane resonator output cavity operating in the “π”-mode. An efficiency of 55% is predicted with a large signal gain near 20 dB by a single particle code which takes into account nonideal effects associated with finite beam thickness and finite magnetic field transition widths. High efficiency is achieved by velocity modulation of an axially-streaming annular beam via a short TM 310 drive cavity. Ballistically created axial bunches are converted into azimuthal bunches when the beam encounters a nonadiabatic, balanced magnetic field reversal at the end of a 30 cm drift region. The design of this tube is presented and its performance is completely characterized before the prospects for the operation of this low voltage configuration at other harmonics are explored View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experimental investigation of a broadband dielectric-loaded gyro-TWT amplifier

    Publication Year: 1996 , Page(s): 1016 - 1020
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    The bandwidth of a gyrotron travelling wave amplifier has been broadened by incorporating a dielectric-loaded interaction waveguide to reduce the circuit's dispersion. This proof-of-principle experiment was designed for the X-band frequency range and operates in the fundamental mode of a rectangular waveguide loaded with dielectric Macor. The amplifier is zero-drive stable and demonstrates a peak output power of 55 kW, 11% efficiency, 27 dB saturated gain with an unprecedented untapered gyro-TWT constant-drive bandwidth of 11% and a saturated bandwidth of 14%. Its performance can be further enhanced by reducing the beam's axial velocity spread as shown by previous simulation studies View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An accurate gate length extraction method for sub-quarter micron MOSFET's

    Publication Year: 1996 , Page(s): 958 - 964
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    By comparing measured and simulated gate-to-source/drain capacitances, Cgds, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the Cgds simulation, the polysilicon gate length, Lpoly, can be accurately determined for device lengths down to the 0.1 μm regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate Lpoly extraction, the source/drain lateral diffusion length, Ldiff , and effective channel length, Leff, can also be determined precisely. The accuracy of Ldiff is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Building-in ESD/EOS reliability for sub-halfmicron CMOS processes

    Publication Year: 1996 , Page(s): 991 - 999
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    MOSFET design in high performance CMOS technologies is driven primarily by performance requirements and reliability issues such as hot carrier degradation. These requirements generally lead to processes that are inherently weak in terms of ESD and EOS. This paper presents a case of building-in ESD/EOS reliability through nMOSFET drain design for a 0.35 μm CMOS process that compromises neither the performance nor the hot carrier reliability. Three process options were considered: nLDD or nDDD ESD implants, and a silicide-block option. The nDDD option for the I/O transistors was chosen as it complied with the performance and reliability (ESD and HCI) specifications and its implementation cost was lower than a silicide-block option. The paper presents data demonstrating the advantages of the nDDD solution over the other alternatives. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout parameters on ESD performance, and hot-carrier data are reviewed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Investigation of hot carrier transport in silicon permeable base transistors

    Publication Year: 1996 , Page(s): 924 - 931
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    The effects of variations in the source to drain distance have been investigated for several highly doped Permeable Base Transistor (PBT) structures. A detailed study of the hot electron transport in these structures is presented using a 2-D self-consistent full band Monte Carlo (MC) simulation program. The PBT structures considered are the overgrown, etched source and etched drain PBT. Finally we have simulated a structure where both the source and the drain have been etched. All structures have a high doping level in the channel (1017 cm-3) and are operating under a gate biasing far from the threshold voltage. The etched structure shows a larger increase in the unity current gain frequency (fT) than the overgrown structure as the source to drain distance decreases. By optimizing the source to drain distance of the etched source PBT, the f T can be increased by a factor of two. Our Monte Carlo result has been compared with an ordinary drift-diffusion (DD) model and a more advanced energy transport (ET) model. The difference between the MC and DD model is largest for the etched structures, while it is less significant for the overgrown structure. However, all structures considered in this work, long and short channel devices, show a larger dc current level in the MC model. This is related to the large electric field and high carrier temperature near the gate depletion region View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Back-gate forward bias method for low-voltage CMOS digital circuits

    Publication Year: 1996 , Page(s): 904 - 910
    Cited by:  Papers (12)  |  Patents (54)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process have been set up against latch-up, parasitic bipolar, impact ionization, and stand by current. Following these guidelines, a cost-effective low power, low-voltage, high-density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

    Publication Year: 1996 , Page(s): 932 - 939
    Cited by:  Papers (20)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi2 on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi2 films were achieved on all narrow, long n+ and p+ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi2 films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n+ and p+ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi2 films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi2 films View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved analog hot-carrier immunity for CMOS mixed-signal applications with LATID technology

    Publication Year: 1996 , Page(s): 954 - 957
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    This paper reports the results of an investigation of hot-carrier effects on analog performance in LATID (Large-Angle-Tilt-Implanted-Drain) and conventional LDD submicron CMOS technology. The investigation focuses on hot-carrier induced degradation of voltage gain, degradation of drain output resistance, and drift of offset voltage of differential pairs. Results illustrate that LATID technology significantly out-performs LDD technology in regard to hot-carrier immunity of key analog parameters in short channel length devices as well as in relatively long channel length devices. The improvement of analog hot-carrier immunity with LATID is attributed to the mechanisms of reduction and departure of high electrical field from the drain area. Results suggest that LATID technology is a promising candidate for mixed-signal ULSI applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel oxide planarization for integrated high-speed Si/SiGe heterojunction bipolar transistors

    Publication Year: 1996 , Page(s): 1036 - 1037
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    A straightforward oxide planarization for double mesa Si/SiGe heterojunction bipolar transistors (HBTs) is presented. The starting point is a bias-sputtered SiO2 film covering a mesa with an auxiliary layer on top. The following planarization is performed only by wet chemical etching. A planarized multiplexer circuit resulted in bit rates up to 18 Gbit/s View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electromigration behavior under a unidirectional time-dependent stress

    Publication Year: 1996 , Page(s): 877 - 882
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    The problem of current induced electromigration in VLSI interconnects, under an arbitrary time-dependent stress, is considered within the drift/diffusion model. It is shown that, by transforming into the convected frame and solving the resulting moving boundary problem, the vacancy build-up may be followed by solving two coupled integral equations. The important large-time behavior is obtained using standard asymptotic techniques. A series solution and an approximate small-time solution are also derived. It is found that, for a unidirectional periodic stress, the equivalent dc current, appropriate to EM reliability tests is the periodic average value. In addition a design rule for arbitrary time-dependent stress is suggested View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New insight in operating modes and optimum design of harmonic TED oscillators for W-band applications

    Publication Year: 1996 , Page(s): 861 - 870
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB)  

    In the present contribution, characteristics of harmonic Gunn oscillators for applications at W-band frequencies are determined by systematic large signal simulations. Based on Monte Carlo (MC) calculations of real active device structures, an accurate full hydrodynamic model has been developed in order to maximize computation speed. An efficient convolution method is used to take the load impedance characteristic of practical resonant mounting structures into account. Investigations of fundamental and harmonic operation with impressed voltages or currents reveal an exceptionally broad range of emitted powers which easily explains varying experimental observations. Numerical results obtained by consistent simulations including the passive load agree well with measurements and allow a deep insight into actual operation principles of the whole oscillator circuit. A preliminary result indicates that even simple Gunn device structures enable power generation at D-band frequencies View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient method for characterizing time-evolutional interface state and its correlation with the device degradation in LDD n-MOSFETs

    Publication Year: 1996 , Page(s): 898 - 903
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    A new characterization method is proposed to study the relationship between the hot-carrier-induced interface state Nit (x) and the device drain current degradation of submicron LDD n-MOSFETs. In this method, by making use of the conventional charge pumping measurement in combination with the power-law dependence of interface damages on stress time, the spatial distribution Nit(x) and the effective damaged length Ldam can be easily extracted. The time evolution of the interface state generation and its correlation with the device degradation can then be well explained. It is worthwhile to note that this newly developed method requires no repetitive charge pumping measurements, and hence avoids he likely imposition of re-stress on tested devices. By combining the characterized Ldam and Nit quantitatively, the results show that the damage at Ldam and VGS≈V DS/2 is most highly localized among various stress biases, which can explain why the generated interface states will dominate the device drain current degradation at this bias after long-term operating conditions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamics of power MOSFET switching under unclamped inductive loading conditions

    Publication Year: 1996 , Page(s): 1007 - 1015
    Cited by:  Papers (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p+ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs

    Publication Year: 1996 , Page(s): 946 - 953
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs is presented, which is based on the well-known resistance method with a special technique to eliminate the uncertainty of the channel length and to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel lengths at an adequate gate overdrive. The 2-D numerical analysis clearly show that adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel doping. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to extract Lmet not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermally robust Ta2O5 capacitor for the 256-Mbit DRAM

    Publication Year: 1996 , Page(s): 919 - 923
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (780 KB)  

    The thermal degradation of the Ta2 O5 capacitor during BPSG reflow has been studied. The cause of deterioration of Ta2O5 with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta2O5 capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Influence of channel doping-profile on camel-gate field effect transistors

    Publication Year: 1996 , Page(s): 871 - 876
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    We report the performance of GaAs camel-gate FETs and its dependence on device parameters. In particular, the performance dependence on the doping-profile of a channel was investigated. In this study, one-step, bi-step, and tri-step doping channels with the same doping-thickness product are employed in camel-gate FETs, while keeping other parameters unchanged, For a one-step doping channel FET, theoretical analysis reveals that a high doping channel would provide a large transconductance which is suitable for logic applications. Decreasing the channel concentration increases the drain current and the barrier height. For a tri-step doping channel FET, it is found that the output drain current and the barrier height remain large and the relatively voltage-independent transconductance is also increased. These are the requirements for the large input signal power amplifiers. A fabricated camel-gate FET with a tri-step doping channel exhibits a large drain current density larger than 750 mA/mm and a potential barrier greater than 1.0 V. Furthermore, the relatively voltage-independent transconductance is as high as 220 mS/mm and the applied gate voltage is up to +1.5 V. A 1.5×100 μm2 device is found to have a ft of 30 GHz with a very low input capacitance View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Relationship between dark carrier distribution and photogenerated carrier collection in solar cells

    Publication Year: 1996 , Page(s): 1034 - 1036
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    The Green's function formalism is used to obtain new theoretical results which establish a simple and quantitative relationship between the spatial dependence of solar cell parameters in the dark and under illumination. It is shown, in particular, that the minority-carrier collection efficiency is equal to a suitably normalized excess minority carrier concentration in the dark View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of fully-implanted NPNs for high-frequency operation

    Publication Year: 1996 , Page(s): 1038 - 1040
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    With a very straightforward (low-cost) process flow as basis, fully-implanted washed-emitter-base (WEB) NPNs have been optimized for operation in the 10-30 GHz range. Above 20 GHz the best overall performance is achieved by heavy doping of the epi. A low-stress silicon rich nitride layer is proven effective as surface isolation before contact window dip-etch View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego