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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Apr 1996

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Displaying Results 1 - 17 of 17
  • 46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology

    Publication Year: 1996 , Page(s): 481 - 486
    Cited by:  Papers (41)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    High-speed multiplexers, demultiplexers, and static frequency dividers are key electronic components in future optical broadband communication systems. In this paper we present a 50 Gb/s multiplexer, a 46 Gb/s demultiplexer, and a 30 GHz static frequency divider. The IC's were fabricated in a self-aligning double-polysilicon bipolar technology using state-of-the-art production process modules. The achieved results are record speeds not only for silicon, but, except for the static divider, for all semiconductor technologies. The high performance of this chipset shows that circuits in silicon bipolar technology will play an important role in future multigigabit-per-second fiber-optic communication systems, at data rates of 20 Gb/s or even at 40 Gb/s View full abstract»

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  • An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

    Publication Year: 1996 , Page(s): 494 - 503
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1804 KB)  

    This paper describes a 16-b fixed point digital signal processor (DSP), especially its multiply-accumulate (MAC) unit, memories, and instruction set. By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAMs. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5-μm double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance View full abstract»

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  • A 286 MHz 64-b floating point multiplier with enhanced CG operation

    Publication Year: 1996 , Page(s): 504 - 513
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1436 KB)  

    This paper presents a high speed 64-b floating point (FP) multiplier that has a useful function for computer graphics (CG). The critical path delay is minimized by using high speed logic gates and limiting the stage number of series transmission gates (TGs). The high speed redundant binary architecture is applied to the multiplication of significands. This FP multiplier has a special function of “CG multiplication” that directly multiplies a pixel data by an FP data. This multiplier was fabricated by 0.5-μm CMOS technology with triple-level metal of interconnection. The active area size is 4.2×5.1 mm2. The operating cycle time is 3.5 ns at the supply voltage of 3.3 V, which corresponds to the frequency of 286 MHz. Implementation of CG multiplication increases the transistor count only 4%. Also, CG multiplication has no effect on the delay in the critical path View full abstract»

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  • A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory

    Publication Year: 1996 , Page(s): 523 - 530
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB)  

    This paper describes an approach to a low power and high speed data transfer scheme in the internal data bus of an AS-Memory which has ASIC circuitry and memory array. Pulse width modulation, which is operated asynchronously, is applied to the wide internal data bus. An automatic gain controlled amplifier which amplifies many small signals from the memory array is also newly developed to achieve a fast data output. Applying this architecture to an AS-Memory, the area and power consumption of the internal data bus interface can be reduced to 25% and 36%, respectively View full abstract»

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  • SOI-DRAM circuit technologies for low power high speed multigiga scale memories

    Publication Year: 1996 , Page(s): 586 - 591
    Cited by:  Papers (5)  |  Patents (131)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty View full abstract»

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  • A 90-MHz 16-Mb system integrated memory with direct interface to CPU

    Publication Year: 1996 , Page(s): 537 - 545
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1396 KB)  

    This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. Also fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-μm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3 mm2 is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-bit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants (PDA's), personal computer systems, and embedded controller applications View full abstract»

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  • A 286 mm2 256 Mb DRAM with ×32 both-ends DQ

    Publication Year: 1996 , Page(s): 567 - 574
    Cited by:  Papers (8)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1400 KB)  

    This paper describes a 256 Mb DRAM chip architecture which provides up to ×32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 μm CMOS technology. The chip measures 13.25 mm×21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85°C. In addition, a 100 MHz×32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated View full abstract»

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  • Driving source-line cell architecture for sub-1-V high-speed low-power applications

    Publication Year: 1996 , Page(s): 552 - 557
    Cited by:  Papers (24)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    A novel SRAM cell architecture for sub-1-V high-speed operation is proposed that uses neither low-Vth MOSFETs nor modified cell layout patterns. A source-line, connected to the source terminals of the driver MOSFETs is controlled so that it is negative and floating in the read and write cycles, respectively. This improved the bit-line access time by 1/4-1/2 at supply voltages of 0.5-1.0 V. Limiting the bit-line swing reduces by 1/10 the writing power needed to charge them and allows faster write-recovery, as well. The achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated View full abstract»

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  • A 2.5-Gb/s 15-mW clock recovery circuit

    Publication Year: 1996 , Page(s): 472 - 480
    Cited by:  Papers (22)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB)  

    This paper describes the design of a 2.5-Gb/s 15-mW clock recovery circuit based on the quadricorrelator architecture. Employing both phase and frequency detection, the circuit combines high-speed operations such as differentiation, full-wave rectification, and mixing in one stage to lower the power dissipation. In addition, a two-stage voltage-controlled oscillator is utilized that incorporates both phase shift elements to provide a wide tuning range and isolation techniques to suppress the feedthrough due to input data transitions. Fabricated in a 20-GHz 1-μm BiCMOS technology, the circuit exhibits an rms jitter of 9.5 ps and a capture range of 300 MHz View full abstract»

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  • Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

    Publication Year: 1996 , Page(s): 592 - 601
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1372 KB)  

    In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced View full abstract»

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  • A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

    Publication Year: 1996 , Page(s): 575 - 585
    Cited by:  Papers (2)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1520 KB)  

    This paper proposes a low voltage operation technique for a voltage down converter (VDC) using a mixed-mode VDC (MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (IAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted by the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the IL-VDC, can be applicable for both low voltage and high frequency operation View full abstract»

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  • Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI

    Publication Year: 1996 , Page(s): 531 - 536
    Cited by:  Papers (13)  |  Patents (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    This paper presents a new circuit scheme called a transient sensitive accelerator (TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively. A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication View full abstract»

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  • A double-level-Vth select gate array architecture for multilevel NAND flash memories

    Publication Year: 1996 , Page(s): 602 - 609
    Cited by:  Papers (32)  |  Patents (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, “A double-level-Vth select gate array architecture” to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized View full abstract»

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  • An efficient charge recovery logic circuit

    Publication Year: 1996 , Page(s): 514 - 522
    Cited by:  Papers (144)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V View full abstract»

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  • A current direction sense technique for multiport SRAM's

    Publication Year: 1996 , Page(s): 546 - 551
    Cited by:  Papers (7)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    This paper describes two techniques for low-power single-end multiport SRAMs: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal, When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40% View full abstract»

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  • Fault-tolerant designs for 256 Mb DRAM

    Publication Year: 1996 , Page(s): 558 - 566
    Cited by:  Papers (15)  |  Patents (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1812 KB)  

    This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm2 256 Mb DRAM with x32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQ's (MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 μA per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intra-block/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield View full abstract»

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  • A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

    Publication Year: 1996 , Page(s): 487 - 493
    Cited by:  Papers (15)  |  Patents (78)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB)  

    A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan