By Topic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • Date Apr 1996

Filter Results

Displaying Results 1 - 9 of 9
  • COP: a Crosstalk OPtimizer for gridded channel routing

    Publication Year: 1996, Page(s):424 - 429
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    The interwire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called crosstalk constraints, are usually given in the design specific... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Addendum to “Synthesis of robust delay-fault testable circuits: Theory”

    Publication Year: 1996, Page(s):445 - 446
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    For original paper see ibid., vol. 11, pp. 87-101 (Jan. 1992). The robust nature of the gate delay fault tests corresponding to Theorems 7 and 8 in the original paper is clarified and described in greater detail. There are two types of robust tests for gate delay faults: a hazard-free robust test for a gate delay fault on a gate g is a robust test where only paths that pass through g are event sen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Incremental layout placement modification algorithms

    Publication Year: 1996, Page(s):437 - 445
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    Many circuit modifications require only a slight adjustment to the IC layouts. General purpose placement algorithms cannot take advantage of these situations because they are designed to generate a complete placement from scratch. In this paper, we present two new algorithms to effect incremental changes on a gate array layout automatically. The algorithms will selectively relocate a number of log... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model

    Publication Year: 1996, Page(s):446 - 451
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A modified Berkeley short-channel IGFET model (BSIM1) has been developed to accurately model the I-V characteristics and circuit performance of deep submicron MOSFET devices. The improved model provides a simple and more efficient parameter acquisition procedure for MOSFET global modeling in comparison to the original BSIM1 model. The procedure for extracting the global geometry scalable model par... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiway VLSI circuit partitioning based on dual net representation

    Publication Year: 1996, Page(s):396 - 409
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1324 KB)

    In this paper, we study the area-balanced multiway partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propose a general paradigm for multiway circuit partitioning based on dual net transformation. Given a netlist, we first compute a K-way partitioning of nets based on the HDN representation, and then transform the K-way net par... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance driven bus buffer insertion

    Publication Year: 1996, Page(s):429 - 437
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    In this paper, we propose a heuristic algorithm for a given topology of a multisource multisink bus to reduce the signal delay time. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. When compared with the traditional method of source driver sizing, experiments show up to 7.2%, 20.7%, and 29.6% improvement in delay for 2.0, 0.5, and 0.3 &mu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions

    Publication Year: 1996, Page(s):385 - 395
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1052 KB)

    This paper presents a new operation (exorlink) and an algorithm to minimize Exclusive-OR Sum-of-Products expressions (ESOPs) for multiple valued input, two valued output, incompletely specified functions. Exorlink is a more powerful operation than any other existing one for this problem. Evaluation on benchmark functions is given and it proves the superiority of the program to those known from the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast factorization method for implicit cube set representation

    Publication Year: 1996, Page(s):377 - 384
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    This paper presents a fast weak-division method for implicit cube set representation using Zero-Suppressed Binary Decision Diagrams, which are a new type of Binary Decision Diagram adapted for representing sets of combinations. Our new weak-division algorithm can be executed in a time almost proportional to the size of the graph, regardless of the number of cubes and literals. Based on this techni... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm

    Publication Year: 1996, Page(s):410 - 423
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1432 KB)

    Automatic test pattern generation (ATPG) yielding high fault coverage for CMOS circuits has received a wide attention in industry and academia for a long time. Mixed level test pattern generation offers advantages, since test generation from gate-level netlists has shortcomings regarding fault coverage in complex CMOS gates. A switch-level approach relying on the transistor structure only is too s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu