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Computers and Digital Techniques, IEE Proceedings -

Issue 2 • Date Mar 1996

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Displaying Results 1 - 9 of 9
  • Evaluating the performance of parallel programs in a distributed environment

    Page(s): 97 - 102
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    Considers methods of evaluating the performance of programs using recent communication harnesses. A demand-based data-farming parallel programming paradigm is used. Possible techniques for performance prediction are examined and a description of a particular method is given, for a shared distributed environment, involving a diffusion approximation. Selected results from a benchmarking study are given to establish the validity of the performance model. A theme of this study is a comparison with a previous transputer-based implementation View full abstract»

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  • Cellular architecture for affine transforms on raster images

    Page(s): 103 - 110
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    Deals with the implementation of 2D affine transform operators as a sequence of window shift operations. The window shift operations shift a specified window by one pixel to either left, right, top or bottom. An architecture dealing with only binary images is proposed for an intelligent video memory which can perform the affine transformations on selected parts of a raster image. The architecture has been simulated and its performance evaluated on a number of sample images. Each window shift operation is executed in one clock cycle which facilitates use of the proposed architecture for real-time applications View full abstract»

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  • Fault-tolerant QRD recursive least squares

    Page(s): 137 - 144
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (772 KB)  

    The authors present an algorithm-based fault tolerant scheme for recursive least squares, appropriate for applications in adaptive signal processing. The technique is closely focused on the Gentleman-Kung-McWhirter triangular systolic array architecture for QR decomposition. Assuming that the array is subject to transient faults, widely separated in time and each affecting a single processor, an algorithm is given that corrects the full triangular array with a computational overhead equivalent, on average, to the interpolation of a single extra vector into the data stream. No output residuals are lost in the fault recovery. The analysis is extended to a fault-tolerant algorithm for linearly constrained QR decomposition View full abstract»

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  • All-fault-tolerant embedding of a complete binary tree in a group of Cayley graphs

    Page(s): 156 - 160
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    The paper solves the problems of fault-tolerant embeddings of a complete binary tree in a group of Cayley graphs. First, a complete binary tree (CBT) is embedded into a complete-transposition graph. Then, the derived result is used to further induce the CBT embeddings for the other Cayley graphs. The primary results are that a CBT with height k×(n-2k+1)+(k-2)×2k+1, where k=[log n], can be embedded into an n-dimensional complete transposition graph (CTn), star graph (STn) and bubblesort graph (BS n) with dilations 1, 3, and 2n-3, respectively. Furthermore, a fault-tolerant scheme is developed to recover multiple faults up to the size of the embedded CBT with the least recovery cost. The dilations after recovery become at most 3, 5, and 2n-1 for the CTn, ST n, and BSn, respectively View full abstract»

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  • BDD-based spectral approach for Reed-Muller circuit realisation

    Page(s): 145 - 150
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    In the past, the use of spectral coefficients the realisation of Reed-Muller circuits led to computational difficulties for functions of even moderate size, due to large memory requirements. A new approach is presented that overcomes these difficulties by allowing the function to be represented using a binary decision diagram, thus reducing the storage requirements, In addition, the computational requirements are also reduced since an efficient method for computing the spectral coefficients is employed. Furthermore, the approach is illustrated with examples View full abstract»

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  • Piecewise estimation of the performability of computer systems

    Page(s): 129 - 136
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    The main objective of the paper is to find acceptable practical methods for evaluating the performability of computer systems. Since the exact evaluation of the performability of such systems becomes intractable as the system grows in dimension and complexity, emphasis is placed on a piecewise estimation that can be obtained with a proposed new numerical procedure. The new numerical procedure is based on randomisation technique which yields a piecewise estimation of the performability (using a Markov reward model) of computer systems. The criteria for choosing a simplified reward structure is addressed and the accuracy of the method is discussed View full abstract»

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  • Application of aggregation strategies in the solution of the optimal routing problem in data networks

    Page(s): 120 - 128
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (860 KB)  

    The paper is concerned with finding acceptable practical methods for evaluating and predicting the performance of data communication networks of arbitrary topologies and complexities. The performance indicator used is the value of the objective function of an optimal routing problem (ORP). Since the exact evaluation of the performance of data networks becomes very time consuming as the system grows in dimension and complexity, emphasis is placed on the reduction in computational time that can be had from the new numerical techniques proposed in the paper. The study of fast approximate solutions is also addressed. In particular, the aggregation policy obtained from a network decomposition algorithm is used to study three strategies for speeding up the solution of the ORP, when using as a baseline, the standard gradient projection (GPM) algorithm. The first strategy, solves a totally, or partially, aggregate network and obtains only approximate results; the second strategy finds a better initial point before starting the standard GPM, and the third strategy considers the application of three different switching mechanisms while the GPM algorithm is in progress. Depending on the traffic and topological characteristics of the network, a saving in computational time of between 10% and 53% can be had when using the acceleration techniques, and a saving of one order of magnitude can be achieved when using the approximation technique View full abstract»

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  • Tradeoff literals against support for logic synthesis of LUT-based FPGAs

    Page(s): 111 - 119
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (856 KB)  

    The paper deals with logic synthesis of lookup-table (LUT) based field-programmable gate arrays (FPGAs). Because each LUT can implement any k input Boolean function with the same area cost, the optimisation criterion of literal count, generally used in other multi-level logic synthesis methods, is not suitable for LUT-based technologies. Therefore a new logic optimisation criterion is proposed, which trades off literals against support. Based on this criterion, five logic operations in logic optimisation are analysed, and made to evaluate the circuit cost in accordance with the target technology. Using these techniques of logic optimisation, a good starting point for technology mapping of LUT-based FPGAs has been obtained. In the technology mapping phase, LUT-directed decomposition is applied. Experimental results indicate that synthesised circuits are much smaller and more routable than the circuits synthesised by other tools View full abstract»

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  • Symbolic method for simplifying AND-EXOR representations of Boolean functions using a binary-decision technique and a genetic algorithm

    Page(s): 151 - 155
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    An algorithm called XORGA is presented which minimises Boolean multi-output logic functions as multilevel AND-EXOR networks of two-input logic gates. It carries out symbolic simplification, and works from the bottom of a binary variable decision tree to the top, with variable choice determined using a genetic algorithm. Since the algorithm is multilevel in nature, it delivers more compact circuits than two-level ESOP minimisation algorithms, such as EXMIN2. It also finds more economical representations than the fixed polarity Reed-Muller method View full abstract»

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