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IEE Proceedings - Computers and Digital Techniques

Issue 2 • Date Mar 1996

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Displaying Results 1 - 9 of 9
  • Symbolic method for simplifying AND-EXOR representations of Boolean functions using a binary-decision technique and a genetic algorithm

    Publication Year: 1996, Page(s):151 - 155
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (444 KB)

    An algorithm called XORGA is presented which minimises Boolean multi-output logic functions as multilevel AND-EXOR networks of two-input logic gates. It carries out symbolic simplification, and works from the bottom of a binary variable decision tree to the top, with variable choice determined using a genetic algorithm. Since the algorithm is multilevel in nature, it delivers more compact circuits... View full abstract»

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  • BDD-based spectral approach for Reed-Muller circuit realisation

    Publication Year: 1996, Page(s):145 - 150
    Cited by:  Papers (4)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (540 KB)

    In the past, the use of spectral coefficients the realisation of Reed-Muller circuits led to computational difficulties for functions of even moderate size, due to large memory requirements. A new approach is presented that overcomes these difficulties by allowing the function to be represented using a binary decision diagram, thus reducing the storage requirements, In addition, the computational ... View full abstract»

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  • All-fault-tolerant embedding of a complete binary tree in a group of Cayley graphs

    Publication Year: 1996, Page(s):156 - 160
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (512 KB)

    The paper solves the problems of fault-tolerant embeddings of a complete binary tree in a group of Cayley graphs. First, a complete binary tree (CBT) is embedded into a complete-transposition graph. Then, the derived result is used to further induce the CBT embeddings for the other Cayley graphs. The primary results are that a CBT with height k×(n-2k+1)+(k-2)×2k+1... View full abstract»

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  • Application of aggregation strategies in the solution of the optimal routing problem in data networks

    Publication Year: 1996, Page(s):120 - 128
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (860 KB)

    The paper is concerned with finding acceptable practical methods for evaluating and predicting the performance of data communication networks of arbitrary topologies and complexities. The performance indicator used is the value of the objective function of an optimal routing problem (ORP). Since the exact evaluation of the performance of data networks becomes very time consuming as the system grow... View full abstract»

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  • Piecewise estimation of the performability of computer systems

    Publication Year: 1996, Page(s):129 - 136
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (808 KB)

    The main objective of the paper is to find acceptable practical methods for evaluating the performability of computer systems. Since the exact evaluation of the performability of such systems becomes intractable as the system grows in dimension and complexity, emphasis is placed on a piecewise estimation that can be obtained with a proposed new numerical procedure. The new numerical procedure is b... View full abstract»

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  • Fault-tolerant QRD recursive least squares

    Publication Year: 1996, Page(s):137 - 144
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (772 KB)

    The authors present an algorithm-based fault tolerant scheme for recursive least squares, appropriate for applications in adaptive signal processing. The technique is closely focused on the Gentleman-Kung-McWhirter triangular systolic array architecture for QR decomposition. Assuming that the array is subject to transient faults, widely separated in time and each affecting a single processor, an a... View full abstract»

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  • Evaluating the performance of parallel programs in a distributed environment

    Publication Year: 1996, Page(s):97 - 102
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    Considers methods of evaluating the performance of programs using recent communication harnesses. A demand-based data-farming parallel programming paradigm is used. Possible techniques for performance prediction are examined and a description of a particular method is given, for a shared distributed environment, involving a diffusion approximation. Selected results from a benchmarking study are gi... View full abstract»

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  • Cellular architecture for affine transforms on raster images

    Publication Year: 1996, Page(s):103 - 110
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (640 KB)

    Deals with the implementation of 2D affine transform operators as a sequence of window shift operations. The window shift operations shift a specified window by one pixel to either left, right, top or bottom. An architecture dealing with only binary images is proposed for an intelligent video memory which can perform the affine transformations on selected parts of a raster image. The architecture ... View full abstract»

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  • Tradeoff literals against support for logic synthesis of LUT-based FPGAs

    Publication Year: 1996, Page(s):111 - 119
    Cited by:  Papers (2)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (856 KB)

    The paper deals with logic synthesis of lookup-table (LUT) based field-programmable gate arrays (FPGAs). Because each LUT can implement any k input Boolean function with the same area cost, the optimisation criterion of literal count, generally used in other multi-level logic synthesis methods, is not suitable for LUT-based technologies. Therefore a new logic optimisation criterion is proposed, wh... View full abstract»

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