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Circuits and Systems, IEEE Transactions on

Issue 1 • Date Jan 1988

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Displaying Results 1 - 17 of 17
  • Parasitic-tolerant components simulation type switched-capacitor filters using unity-gain buffers

    Page(s): 35 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    Novel switched-capacitor transconductance elements that are free from resistive effects due to parasitic capacitances are used to realize the filters. The absence of resistive parasitics lowers the overall parasitic sensitivity of such filters. The remaining small deviations in the response can be overcome by simple predistortion. Computer simulation on a sixth-order bandpass filter is presented View full abstract»

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  • Adaptive schemes for noise filtering and edge detection by use of local statistics

    Page(s): 57 - 69
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1988 KB)  

    Some adaptive schemes for noise filterings and edge detection of digital signals are developed. They are bases on the minimum-mean-square-error estimate of the information-bearing signal corrupted by additive noise. The estimate is computed using the local statistics of the input signal and noise. The output is fed back to the input, and the difference between the input and the output is used as the noise estimator. The local statistics of signal and noise are computed through a moving signal window and a moving noise window, which are over the input signal and the noise estimator, respectively. These schemes change their performance according to the local signal-to-noise ratio adaptively. Two kinds of adaptive filtering algorithms and an edge detection algorithm are considered. Their performance in the presence of noise is evaluated and compared to the performance of some other methods. Simulation results on one-dimensional signals and real images are presented View full abstract»

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  • Arbitrary phase polynomials for sampled-data systems

    Page(s): 132 - 133
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    A simple method is proposed for generating a polynomial of degree n to match a prescribed phase at a specified set of frequencies on the unit circle in the Z-plane. This class of polynomials is very useful for designing recursive digital filters with flat group delay or linear phase. The proposed polynomials are easy to adopt for designing all-pass digital circuits View full abstract»

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  • Structure of the submarking-reachability problem and network programming

    Page(s): 89 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1032 KB)  

    Using a linear programming formulation, a unified treatment of the submarking-reachability problem for both capacitated and uncapacitated marked graphs is presented. In both cases, the problem reduces to that of testing feasibility of the dual transshipment problem of operations research. An algorithm called REACH is presented for the feasibility testing problem; its worst-case time complexity is O(mn), where m and n are, respectively, the number of edges and the number of nodes in the marked graph. The place of this work in the context of general network programming problems is indicated View full abstract»

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  • Modified stability table for 2-D digital filters

    Page(s): 116 - 119
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    A modified stability table is obtained for checking the stability of 2-D digital filters. In this table, the appropriate entries of the first column are equivalent to the appropriate minors of the Hermitian Schur-Cohn matrix. Thus the positivity of the latter matrix requires the positivity checking of the (n-1) appropriate entries for one point, and the last entry, which is equivalent to the Schur-Cohn determinant, is to be checked for positivity for all |z|=1. This test is simpler than several others appearing in the literature View full abstract»

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  • Circuit partitioning simplified

    Page(s): 2 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    The key concepts of `tearing' are presented. Tearing is a means of circuit partitioning with a formal mechanism for piecing together the subcircuit solutions to yield the composite result. The implications of a single `torn' element are examined, and the pertinent results for multiple partitioning are discussed View full abstract»

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  • Adaptive algorithms with an automatic gain control feature

    Page(s): 122 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    An automatic gain control (AGC) scheme is introduced for adaptive algorithms that are used extensively in many applications. The scheme is realized by using an estimate of the cross correlation between the adaptation error and the input signal to control the gain of the adaptive algorithm. When the cross correlation is high, the gain is also high, and the adaptive algorithm is in an `active' state. When the error and the input signals are uncorrelated, the gain is closed to zero, and the adaptive algorithm is put in an `asleep' state. Thus, adaptive algorithms with such AGC are comparatively insensitive to disturbances appearing on the system output measurement, which can drive conventional adaptive algorithms away from the achieved adaptation. A fast, efficient algorithm for estimation of the cross-correlation coefficient of adaptive error and input is proposed View full abstract»

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  • A nonlinear adaptive digital filter

    Page(s): 127 - 131
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    An adjustable, memoryless, single-valued, monotonic nonlinearity is introduced between the output point of a linear adaptive FIR (finite-impulse response) filter and the output point of the system. A control strategy is derived that permits the simultaneous shaping of both the power spectrum and the amplitude-density function of the system output by jointly adjusting the shape of the nonlinearity and the tap weights of the linear filter. A mechanization diagram and some mechanization considerations are presented View full abstract»

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  • Design of computationally efficient interpolated FIR filters

    Page(s): 70 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1536 KB)  

    The number of multipliers required in the implementation of interpolated FIR (Finite-impulse response) filters in the form H(Z)=F(zL)G( z) is studied. Both single-stage and multistage implementations of G(z) are considered. Optimal decompositions requiring fewest number if multipliers are given for some representative low-pass cases. An efficient algorithm for designing these filters is described. It is based on iteratively designing F(z L) and G(z) using the Remez multiple-exchange algorithm until the difference between the successive stages is within the given tolerance limits. A novel implementation for G(z) based on the use of recursive running sums is given. The design of this class of filters is converted into another design problem to which the Remez algorithm is directly applicable. The results show that the proposed methods result in significant improvements over conventional multiplier efficient implementations of FIR digital filters View full abstract»

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  • Loss-free gyrator realization

    Page(s): 26 - 34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    A loss-free time-variable gyrator (TVG) based on the power-out-equals-power-in (POPI) concept is presented. The POPI is a `black box' without source elements, in which the instantaneous output power equals the input. A method based on a controlled time-variable transformer is presented, and it is noted that based on the same method, transformer realization by means of a single-controlled gyrator can be achieved. Synthesis based on switched-mode power conversion circuits is discussed. A gyrator consisting of such a circuit has been constructed View full abstract»

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  • Modular architectures for two-dimensional digital signal processing

    Page(s): 43 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    The implementation of highly modular two-dimensional (2-D) digital filters is addressed. The idea of matrix decomposition is used to provide increased parallelism and regularity. Four different structures, namely, the transversal, the distributed arithmetic, the stored product, and the systolic array, are considered. For comparison purposes, the direct implementation is included. An analysis of each of each is performed and comparisons are made in terms of hardware cost, cycle time, finite register length effects, and regularity. It is found that the systolic array structure seems to offer the best compromise among the various conflicting figures of merit. The distributed arithmetic structure is shown to be superior in the case of low-order filters, while the stored product structure is preferable for high-order filters. The inherent parallelism and high throughput rate of these structures make them suitable for real-time image processing applications View full abstract»

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  • Analysis and correction of VLSI delay measurement errors due to transmission-line effects

    Page(s): 19 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    In the testing of VLSI chips that have more than 128 pins, it is necessary to measure the signals from the devices under test (DUT) at the far end of transmission lines 50 cm or more away from the contact pads. The measurement suffers form waveform distortions and errors that are caused by the intrinsic delay of the transmission lines and the loading conditions at both ends of the transmission lines. This problem is analyzed using mathematical models, and the results are applied to correct the measurement errors with computer aid. A technique is presented to evaluate the true output delay time of the DUT under specified loading conditions, using the measured data from an imperfect measurement setup. Computer simulation results indicate that this technique is accurate and can be applied to practical VLSI measurements View full abstract»

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  • Floating point error analysis of two-dimensional, fast Fourier transform algorithms

    Page(s): 112 - 115
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    Floating-point error is conducted for three algorithms commonly used for the calculation of two-dimensional fast Fourier transforms (FFTs), namely, the conventional row-column FFT, the vector-radix FFT, and the polynomial-transform FFT. The respective errors are determined both analytically and on the basis of computer simulation. Comparison shows that the vector-radix FFT and the polynomial-transform FFT, even though computationally more efficient than the row-column FFT, show approximately the same (and sometimes reduced) susceptibility to errors in floating-point arithmetic View full abstract»

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  • Triple matrix product architectures for fast signal processing

    Page(s): 119 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A procedure is introduced to determine highly concurrent representation of linear algorithms. The technique replaces matrix/vector operations by sums of small-size triple matrix products. A specially dedicated array architecture performs each triple product without intermediate I/O operations. The highly concurrent representation is shown to be possible for any linear algorithm. The special architecture features dual-mode operation for processing elements and closed-loop data circulation. Both characteristics increase the flexibility and speed of the configuration View full abstract»

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  • Nonlinear echo cancellers based on transpose distributed arithmetic

    Page(s): 6 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    The design and performance of an echo canceller used in a full-duplex multilevel digital baseband transmission system are described. The system suffers from mild nonlinearity due to tolerancing of analog components in its transmitter. The nonlinearity is dealt with in the echo canceller by recourse to a nonlinear adaptive filter based on the use of transpose distributed arithmetic. Filter structures allowing fast startup techniques that use known bounds on the nonlinearities are evaluated. The theoretical performance of the filters is examined, and the extrapolation of classical linear theory is shown to provide an insufficient description of the filters' behavior. A novel state-variable-analysis technique is introduced and shown to provide a complete description View full abstract»

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  • Systolic array implementation of H(z-1)=(a0+a 1Z-N+a2Z-2N)/(1+b1 Z-N +b2Z-2N) for N⩾2

    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB)  

    A novel systolic array for the implementation of a second-order IIR (infinite-impulse response) transfer function expressed in terms of Z-N is presented. The array is suitable for any value of N greater than or equal to two. The major advantages of this systolic array include nearest-neighbour interconnection and a requirements of only three identical basic cells View full abstract»

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  • Canonical piecewise-linear representation

    Page(s): 101 - 111
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    Every continuous piecewise-linear function of one variable f :R1R1 has a unique canonical piecewise-linear representation. However, only a subclass of higher-dimensional piecewise-linear functions f:RnRn, n>1, has a canonical piecewise-linear representation. It is proved that the necessary and sufficient conditions for the existence of a canonical piecewise-linear representation is that fpossess a consistent variation property. The geometrical constraints imposed by this property are analyzed and discussed in detail along with many examples View full abstract»

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