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Circuits, Devices and Systems, IEE Proceedings -

Issue 5 • Date Oct 1995

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Displaying Results 1 - 11 of 11
  • Multiple-inputs systolic priority queue for fast sequential decoding of convolutional codes

    Page(s): 282 - 292
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (972 KB)  

    The operating speed of a sequential decoder with stack algorithm is usually limited by the time to search the best node for further extension. This problem can be completely alleviated by using the systolic priority queue to replace the stack memory. However, the systolic priority queues developed previously are accessible only in the cases when the number of inputs processed is small. This is because the complexity of a queue grows up quickly as the volume of data flowing through it increases. Since the largest amount of data flowing through a systolic priority queue is equal to the number of inputs to this queue, the systolic priority queue is not suitable for a system with many inputs. A modified version of previously developed circuits is proposed. The number of transmission gates required in this circuit is proportional to 3N instead of N2, where N is the number of inputs. Also the total number of control signals is proportional to 3N 2 instead of N3. But the number of comparators required is proportional to C2N+1, as before. This modified circuit can be used in cases where the number of inputs is small (N⩽8). A new algorithm for the multiple-inputs systolic priority queue (MISPQ) is proposed. By using this algorithm, a MISPQ may be implemented with several smaller queues, each is used to process a part of data in the MISPQ. Since the volume of data flowing through each queue is small, these queues will be simpler. However, some additional circuits should be used for the interactions between queues. A circuit for implementing this algorithm is presented and its complexity is analysed. The number of transmission gates for the MISPQ is proportional to 3N, the number of control signals is proportional to (3N2/2), and the number of comparators is proportional to 4C 2N/2+1. Thus this new architecture is feasible for large N (e.g.N⩾8) View full abstract»

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  • Simple allpass sections with complex poles and zeros

    Page(s): 273 - 276
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A simple generation and synthesis method of a second-order allpass function with complex poles and zeros is presented. Networks are realised with only one operational amplifier and simple RC one-ports. The effect of the limited gain and passband of the amplifier on the frequency and Q-factor of the poles is also discussed View full abstract»

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  • Effects of response quantisation on the accuracy of transient response test results

    Page(s): 334 - 338
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    Transient response testing has been shown to be an economical technique for testing linear macros in mixed-signal systems. Previously reported work on the analysis of transient responses has shown how the response from a linear network can be processed to generate a single figure, termed the index of functionality, which is an absolute measurement of device functionality and on which pass/fail decisions are subsequently made. However, if the circuit response is deeply buried in the mixed-signal system, it must first be extracted before it can be processed. The paper details the results of an investigation into the effects of sampling, quantising and extracting transient responses serially through a digital scan path before processing. By understanding the mechanisms by which errors introduced by the sampling and quantisation process manifest themselves in the index of functionality, it is possible to optimise the quantisation parameters for a particular test situation and test to any required standard View full abstract»

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  • Determination of the RF-noise source parameters in AlInAs/GaInAs-HEMT heterostructures based on measured noise temperature dependence against electric field

    Page(s): 339 - 344
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The noise temperature dependence on the electric field in an AlInAs/GaInAs-HEMT heterostructure has been measured. It was found that the dependence of the noise temperature on the electric field in GaAs-MESFETs and in AlInAs/GaInAs-HEMTs is remarkably different. For this reason a different model must be used for AlInAs/GaInAs-HEMTs. Based on the measured noise temperature dependence on the electric field, an analytic noise model for the AlInAs/GaInAs HEMT has been developed. The noise source parameters were calculated and compared with extracted noise source parameters from noise measurements View full abstract»

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  • Analysis and modelling of parasitic substrate coupling in CMOS circuits

    Page(s): 307 - 312
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed View full abstract»

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  • Modelling of gas-sensitive conducting polymer devices

    Page(s): 321 - 333
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1088 KB)  

    Recent studies have shown that conducting polymers are sensitive to a wide range of gases and vapours and may be used in gas-sensing microelectronic devices. The authors present a basic model for polymer gas sensors which consists of a thin uniform polymer film lying on top of a pair of either semi-infinite or finite coplanar electrodes supported by an insulating substrate. It is assumed that the gas, or vapour, diffuses into the film and is, simultaneously, adsorbed at sites randomly distributed throughout the film. The diffusion and adsorption equations are presented in terms of several fundamental dimensionless parameters which describe the underlying chemical and physical properties of the system. Numerical solutions to the equations are calculated for both the gas and adsorbate profiles within the films at various times. These numerical solutions are compared with approximate analytical expressions previously derived for diffusion-rate limited, reaction-rate limited and intermediate cases, and show good agreement. Finally, a semiconductor model of electronic conduction in gas-sensitive polymer films is developed to calculate the theoretical device response to the sorption of organic vapours. This model can be used to investigate the effects of device geometry on sensor response and is therefore a useful design tool for evaluating novel device structures. The model may also be extended to cover other types of device, such as capacitive or mass balance View full abstract»

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  • Hybrid knowledge-based system/multilayer perceptron approach for the post-assembly tuning of electronic filters

    Page(s): 277 - 281
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    A generic approach to the development of a hybrid knowledge-based system (KBS)-multilayer perceptron (MLP) system for the post-assembly tuning of filters is described. This KBS uses rules derived using the Iterative Dichotomiser 3 to advise upon which filter component to adjust and in which direction. The problem is divided into a number of search spaces corresponding to three levels of decision, and numerical attribute values are represented by numerical ranges with logical names. How far to turn is determined by a set of MLPs, trained on the amplitude responses of a typical filter. It is established that the task requires a hybrid system and cannot be satisfactorily performed by either a KBS or MLP alone. When applied to the amplitude response tuning of four-pole asymmetric bandpass crystal filters three adjustments are typically required, on average, to tune the stopbands of 79% of those tested. The lengthy development times needed per filter type of 1-2 weeks are compensated for as the task is within the capabilities of a trained operator View full abstract»

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  • Multiple-valued logic network using quantum-device-oriented superpass gates and its minimisation

    Page(s): 299 - 306
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    A superpass-transistor (SPT) model is presented as a quantum-device candidate for future VLSI systems based on multiple-valued logic (MVL). A conceptual SPT structure based on the ideas of a lateral-resonant-tunnelling quantum-dot transistor (LQT) and a heterostructure FET is described. An important feature of the SPT is its capability of MVL signal detection and generation. A superpass gate (SP gate) corresponding to a single SPT is defined and is demonstrated to be a universal logic module for implementing highly compact multiple-valued VLSI systems. An algorithm suitable for synthesising minimal series-parallel SP-gate networks for MVL functions with many variables is proposed. The network allows both constants and variables as its pass inputs; accordingly, υ-subfunctions, where υ can be a constant or a variable, are defined. SP implicants, SP subimplicants and the consensus between SP subimplicants are also defined. The algorithm first generates all prime SP subimplicants from υ-subfunctions by using the consensus operation, then derives all prime SP implicants by using the implication operation, and finally selects an optimal set of prime SP implicants to cover the function by using existing methods View full abstract»

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  • VLSI architectures for computing X mod m

    Page(s): 313 - 320
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    The implementation of residue number system based arithmetic processors has been made feasible by the recent developments in microelectronics. New VLSI architectures are proposed for computing the integer module operation X mod m, when m is restricted to the values 2 k, 2k±1 and composite numbers whose mutually prime factors fall in the above category. Two different design methodologies, namely the recursive and partition methods are presented, and their respective VLSI computational complexities are analysed. A VLSI chip that computes X mod m, where X is a 16-bit number and m=3, 5, 6, 7, 9 and 10, has been implemented using the proposed schemes in 3 μm CMOS technology, and typical measurements have yielded a propagation delay of less than 109 ns View full abstract»

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  • Distortion analysis of nonlinear systems with memory using maximum-length sequences

    Page(s): 345 - 350
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    Crosscorrelation using a binary MLS excitation yields a linear system response, whereas system nonlinearity produces a residue dispersed over the MLS period. By incorporating precomputed templates, coefficients of a nonlinear polynomial descriptor can be decoded from this distortion residue, and, by incorporating complex coefficients, nonlinearity with memory can be accommodated. A nonlinear model results from which general THD and IMD can be derived from a single MLS measurement View full abstract»

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  • Issues in the design of a logic simulator: an improved caching technique for event-queue management

    Page(s): 293 - 298
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    The paper describes certain issues relevant to the development of a logic simulation engine, designed to be incorporated into a mixed-signal simulator. Usually, the rate-limiting process in any mixed-signal simulation is the analogue processing but, for systems with a significant asymmetry between logic and analogue components, the efficiency of the logic engine can obviously become important. A technique is reported for improving both the space and time complexity of the logic engine: a method of event-queue searching using multiple cache pointers. Experimental results show that about five cache pointers provide the optimum efficiency gain from this technique. Finally, problems of event-queue management are reviewed, with particular reference to the situation where simulation time is represented by a real number, as it must be in a mixed-signal environment View full abstract»

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