IEEE Design & Test of Computers

Issue 1 • Spring 1996

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Displaying Results 1 - 10 of 10
  • East Meets West [Guest Editors' Introduction:]

    Publication Year: 1996
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    Freely Available from IEEE
  • Frequency domain testing of ADCs

    Publication Year: 1996, Page(s):64 - 69
    Cited by:  Papers (37)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (604 KB)

    Aimed at design and test engineers making the transition from strictly digital devices to devices with both digital and analog content, this tutorial introduces frequency domain analysis for the testing of mixed-signal devices. The author describes dynamic testing of analog-to-digital converters using Fourier analysis, including coherent sampling techniques. He also covers the challenges of implem... View full abstract»

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  • Sensitivity analysis of critical parameters in board test

    Publication Year: 1996, Page(s):58 - 63
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    The authors analyze the main contributors to the quality and cost of complex boards. With manufacturing data from Hewlett-Packard boards, they use simulation models to derive the sensitivity of quality and cost to the solder defect rate, the functional defect rate, and test coverage. They also give a simple cost estimate of implementing IEEE 1149.1 boundary scan on ASICs. Their new yield model, wh... View full abstract»

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  • Self-checking design in Eastern Europe

    Publication Year: 1996, Page(s):16 - 25
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1488 KB)

    This survey introduces the design concepts of self-checking circuits and discusses research activities in on-line hardware-checking techniques developed in Eastern Europe, including the former Soviet Union. Many of the research results appeared in journals and conference proceedings previously unavailable to Western researchers View full abstract»

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  • Intel and the myths of test

    Publication Year: 1996, Page(s):79 - 81
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (376 KB)

    The author describes device testing at Intel, a company that tests 50 million microprocessors a year. He notes some myths that have grown up around testing and addresses the challenges facing test engineers, test system designers, and researchers View full abstract»

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  • Test synthesis with alternative graphs

    Publication Year: 1996, Page(s):48 - 57
    Cited by:  Papers (60)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1220 KB)

    Alternative graphs provide an efficient, uniform model describing the structure, functions, and faults in a wide class of digital circuits and for different representation levels. For test pattern generation, they provide a general theoretical basis for combining high-level approaches, symbolic techniques based on binary decision diagrams, and traditional topological algorithms View full abstract»

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  • Verifying timing consistency in formal specifications

    Publication Year: 1996, Page(s):8 - 15
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1180 KB)

    The authors' algorithm formally verifies the rule set that expresses timing discipline in digital system specifications. Their algorithm is based on a higher level behavioral specification model and concerns formal consistency verification at the design level of the system specification development procedure View full abstract»

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  • Fast power estimation of large circuits

    Publication Year: 1996, Page(s):70 - 78
    Cited by:  Papers (25)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1340 KB)

    Our new technique for estimating transition probabilities of internal signals in combinational circuits uses Markov chains and reconvergence regions. To efficiently implement the computation, we use ROBDDs (reduced, ordered binary decision diagrams). Accounting for temporal dependence of signals, multiple concurrent transitions, and mutual dependence of internal signals, the technique provides an ... View full abstract»

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  • Net scheduling in high-level synthesis

    Publication Year: 1996, Page(s):26 - 35
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1296 KB)

    A new net scheduling and allocation model generates net schedules that minimize either execution time or resources. The author tested the model within a VHDL-based high-level synthesis system called Ahiles View full abstract»

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  • Interconnection problems in modern computers

    Publication Year: 1996, Page(s):36 - 46
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2544 KB)

    Interconnection problems that designers could neglect become significant in high-speed computers. At high frequency, interconnections act as transmission lines; modeling them as lumped circuits is incorrect. Thus, early accounting for interconnection problems is essential to a competitive design View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty