By Topic

Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on

Issue 1 • Date March 1996

Filter Results

Displaying Results 1 - 20 of 20
  • Foreword Advanced Interconnects and Materials

    Save to Project icon | Request Permissions | PDF file iconPDF (159 KB)  
    Freely Available from IEEE
  • Foreword Thermal Design and Analysis

    Save to Project icon | Request Permissions | PDF file iconPDF (66 KB)  
    Freely Available from IEEE
  • Characteristics and potential application of polyimide-core-bump to flip chip

    Page(s): 18 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1496 KB)  

    Polyimide core bumps are formed by following these steps: first, forming polyimide cores using photosensitive polyimide, next, metallization on the polyimide cores by sputtering, and finally, patterning the metallized layers. The polyimide core bumps thus prepared have the advantages of larger aspect ratios, and better bump height uniformity without conventional levelling process, and larger elasticity compared with solid metal bumps such as gold or solder. Also various bonding methods are applicable as solderings, or gold-tin bonding with pressure and adhering, or other mechanical contact with adhesive View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal solutions to Pentium processors in TCP in notebooks and sub-notebooks

    Page(s): 54 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1396 KB)  

    In this paper, we will review the various thermal enhancements from the component, board, and system level for the use of the Pentium processor in tape carrier package (TCP) in notebooks and sub-notebooks. The thermal tests were conducted in one reference notebook and sub-notebook using test boards and thermal test dies. With the assumption of a maximum junction temperature of 100°C and an outside ambient temperature of 35°C, thermal characterizations of TCP found that with 4 W of board power, TCP can dissipate up to 3.55 W of CPU power in the reference notebook and 2.72 W in the reference sub-notebook. Various thermal enhancements such as venting holes, metal plates, and heat sinks were evaluated in the reference notebook. For the design target of 6.5 W of CPU power with 4 W of board power, four thermal solutions were proposed for the reference notebook: The heat sink and aluminum plate solution, heat pipe connected to the keyboard solution, heat pipe connected to outside aluminum plate solution, and fan/heat sink solution. Two solutions were proposed for the reference sub-notebook: The heat pipe connected to keyboard solution and heat pipe on the bottom chassis solution. Although the study was conducted in the reference notebook and sub-notebook, the thermal design trade offs and relative cooling capabilities are applicable to the general notebook and sub-notebook thermal designs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Silicon motherboards for multichannel optical modules

    Page(s): 34 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1448 KB)  

    A novel method of a fluxless, high precision, and reliable Au/Au thermo compression flip chip bonding process for optoelectronic devices has been developed. The main technologies for the manufacturing of multichannel optical modules are based on the height control within 0.5 μm of electroplated Au bumps on silicon motherboards in the close environment of v-grooves, the flip chip bonding applying low pressure at temperatures below 300°C, and reproducible passive fiber array alignment with high coupling efficiencies. A coupling loss of 8.5 db has been achieved, which is very close to the active alignment result of 8.1 dB. The reliability of flip chip bonded laser and photo diodes has been investigated by aging and temperature cycling tests, where no shift of the threshold current occurred, the coupling efficiency did not vary and the dark current showed no degradation. The RF performance of the electrical interconnection on the silicon motherboard has been analyzed and a transmission experiment at 622 Mb/s has been done successfully View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Influence of microstructure on dielectric strength of CuCr contact materials in a vacuum

    Page(s): 76 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB)  

    The influence of microstructure of CuCr contact materials on dielectric strength in a vacuum is investigated. Experimental results show that breakdown selectively occurs on dielectrically weak phases. For the Cu50Cr50 alloy, it first takes place on Cr particles, and for the CuCr50Sel alloy, on the Cu2Se phase. As a result of conditioning of breakdown, the dielectric strength of these phases increases, and breakdown occurs simultaneously. Breakdown roughens the surface of the cathode, but produces a small melt layer on the surface which has much finer microstructures and more homogeneous microcompositions. The effect of conditioning of breakdown to increase dielectric strength, according to the present work, is to produce much finer microstructures and more even micro-compositions on the contact surface View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new approach to using anisotropically conductive adhesives for flip-chip assembly

    Page(s): 5 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1052 KB)  

    The use of anisotropically conductive adhesives (ACAs) for the direct interconnection of silicon chips to printed circuits offers numerous advantages including: reduced package thickness, improved environmental compatibility, lowered assembly temperatures, increased metallization options, and decreased equipment needs. To increase throughput and to lower costs, we have developed a new approach to flip-chip assembly with ACAs. Our process uses two unique features: an ACA thixotropic paste formulation and a batch curing fixture. The thixotropic paste, which replaces the more conventional film form of the adhesive, can be easily dispensed onto the substrate with a stencil printer. Chips placed into the ACA paste are held securely due to the “tacky” nature of the material much like surface mount components are held by solder pastes. As a result, no heating of the chips is required during assembly, increasing throughput and relaxing co-planarity tolerances in the alignment equipment. As with all ACAs, the paste must be cured by the simultaneous application of heat and pressure. In our process, curing is accomplished in a fixture capable of holding multiple chips and/or circuit boards simultaneously. Uniform pressure is applied to components during the 3-5 min thermal cure cycle via a conformable silicone rubber bladder. Initial yield and temperature cycling data are reported in this paper. Silicon chips with gold metallization show small (<15%) increases in contact resistance after more than 1000 test cycles (between 0-100°C); bumping the chips was not required. Aluminum metallized chips proved to be unreliable after temperature cycling tests View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New contact design for the ex situ fabrication of small size, low resistivity normal metal contacts to epitaxial c-axis YBCO films

    Page(s): 105 - 112
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1108 KB)  

    We report a new method for the ex situ fabrication of low resistance ohmic contacts between planar epitaxial c-axis YBCO films and Ag/Au metallizations. The process involves the etching of slots into the superconductor prior to metal deposition and annealing at 450°C. We confirmed the optimum dimensions of the superconductor line and slot width to be 1 μm. The patterning processes were investigated which permitted us to fabricate these dimensions with no discernible degradation of the high temperature superconductors (HTSC) edges and surface degradations below 30 nm thickness. Specific contact resistivities in the 10-6...10-7 Ω·cm 2 region have been achieved which is an advantage over planar contacts of up to two orders of magnitude and can be obtained for contact pads of widths above 10 μm. Contacts provided with slots are characterized by a significant increase in homogeneity and reproducibility compared to annealed planar contacts. The temperature and size dependence of the contact resistances of planar and slotted contacts have been compared and studied as a function of film morphology and contact metal. The resulting contact resistance can be related to the interface resistance in band c-directions as well as to the formation of point contacts and a contribution of the spreading resistance of the contact layer View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mechanical response of PCB assemblies during infrared reflow soldering

    Page(s): 127 - 133
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    A finite element structural model is developed to predict the thermomechanical behavior of printed circuit board (PCB) assemblies during infrared reflow soldering. Specifically, the model predicts the amount of board warpage, the effects of increased PCB assembly stiffness resulting from the solder joint formation, and the size of gaps generated at the module lead solder pad interface. In this paper, quantitative estimates of these process-induced variables are provided as well as a description of the approach used for the analyses View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliability investigations of fluxless flip-chip interconnections on green tape ceramic substrates

    Page(s): 24 - 33
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1888 KB)  

    The use of flip chip bonding technology has a growing importance in the construction of novel hybrid microelectronic devices and is of increasing interest for the application in consumer oriented products. Fluxless processes, especially, are demanded for the compatibility with underfill materials and for an improved reliability performance This paper describes the development of a fluxless flip chip mounting process by use of Au/Sn solder bumps on different thick film metallizations of green tape ceramic substrates. The results of the investigations show that fluxless flip chip bonding is possible directly on Au as well as Ag and Pd/Ag thick film pattern and via metallizations. The flip chip assembly process is performed by single chip bonding and requires substrates with narrow planarity tolerances. For the different substrate metallizations, the range of optimal bonding parameters are determined. Best mechanical and electrical results are achieved with Au/Sn bumps on Pd/Ag thick film metallizations. For this system, the investigations are performed to show the influence of the chip size and bump height on reliability. The fatigue life of solder joints, which is limited by the thermal expansion mismatch between chip and substrate, could be significantly increased by an adequate encapsulation process. The reliability results of the fluxless flip chip joints after thermal cycling, temperature storage, temperature-humidity, and pressure cooker tests are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal sensitivity analysis for the 119 PBGA-a framework for rapid prototyping

    Page(s): 66 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1124 KB)  

    New package prototyping is often a sequential process where the chip and system parameters are specified first, then the package design is initiated. A reduction in overall cycle time can be affected if the events occur simultaneously. This study proposes a methodology for addressing this issue. The method is outlined in the context of prototyping the 119 plastic ball grid array (PBGA) package thermal performance. The parameters influencing performance are system, device, or package based. Ranges for the “yet-to-be-fixed” parameters are determined and factorial analyses are used to yield approximate linear models with interactions for package performance. Once the device and system parameters are “fixed”, the linear equations are solved simultaneously with junction and board temperature constraints to yield a design options map for package layout. The prototyping sequence for the PBGA results in substrate thermal conductivity, mother board thermal conductivity, mother board load, and heat sink attachment as the set of “variable” parameters-with other parameters being “fixed”. The design options map gives the minimum substrate thermal conductivity needed to meet the thermal performance specification for a particular set of parameters. The substrate specification is further related to physical attributes required of the package in terms of thermal vias, thermal bumps and metal layers. These results are generically applicable to the PBGA family. A 119 PBGA package enclosing a 2 W chip requires a minimum substrate thermal conductivity of 0.03 W/cm-°C to meet the junction temperature constraint for high performance workstation environments. Results of the performance prediction are further verified by a composite finite element simulation and experimental validation with prototypes. The design options map can be recreated without any additional simulation studies in the event any change in the “fixed” parameters occurs. The methodology described allows anticipation of design options in the “dynamic” environment of prototyping, and implementation of optimized package designs to meet performance under multiple customer environments View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Availability of Al-Mg alloys for use as electrical contact resistors

    Page(s): 98 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    Fretting experiments associated with contact resistance were carried out with Al-Mg alloys (Al-3wt%Mg and Mg-3wt%Al). It was found that the contact behavior of these alloys is considerably different; the saturation value is 2.5 mΩ at a load less than 1N for A-3wt%Mg irrespective of humidity and has almost the same value (3 mΩ) at 2N with a relative humidity under 30%RH for Mg-3wt%Al. The number of cycles at the saturation value of the contact resistance in Mg-Al decreases with increasing humidity. The analysis of the fretted surface with electric current showed that the X-ray diffraction intensity of MgO formed during fretting in Mg-Al increases monotonously with the increase of the relative humidity, but in samples without electric current there is a transition giving a maximum at about 50%RH. These results make it clear that the wear behavior is subject to the electrical contact condition in each alloy. On the basis of the experimental results, the effects of Mg (or Al) as an Al (or Mg) additive on the electrical contact property are discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mounting of high power laser diodes on diamond heatsinks

    Page(s): 46 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    This work describes the mounting of commercial 1 W laser diodes soldered on chemical vapor deposition (CVD) diamond heatsinks using Au(80)Sn(20)-solder. With a standard heatsink metallization, the laser diode suffers under high stress. This can be seen in the power-current characteristic and the spectrum as well as in the near and farfield beam pattern, With a modification of the heatsink metallization layer, it was possible to obtain a reproducible mounting process. We compare the electrical and optical characterization of the typical standard heatsink metallization with the modified metallization. So we are able to qualify the mechanical stress in the laser diode. For a better understanding of the modified metallization SEM and EDX analyses are performed. For the quantification of the stress an analytical model is used to compute the maximal shear, tensile, and peel stress. Furthermore, the quality of the bond interface is investigated with high resolution X-ray microscopy. No voids are found. Additionally, the results of a standard burn-in and the first accelerated aging tests to prove the reliability are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Gold wire bonding onto flexible polymeric substrates

    Page(s): 12 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    As part of a program to develop very thin, low cost packages using available technology, copper clad polymeric materials were examined as potential substrates for high temperature wire bonded chip-on-flex circuits. New thermoplastic flex and a PTFE/woven glass substrate were evaluated along with polyimides using high temperature copper laminate adhesives and adhesiveless constructions. Initial wire bond pull tests indicated all the materials were suitable for high speed gold wire bonding. Similarly, conventional glob top encapsulants were found to adhere to each of the 13 substrates tested; experimental UV curable glob top materials were found to adhere well to polyester and PTFE substrates, but not to polyimides or polyether imides. Electrical test vehicles were constructed of gold wire bonded daisy chain chips on low cost polyimide substrates. Temperature cycling and thermal shock data showed no increase in circuit resistance for packages using commercial encapsulant formulations as well as using a formulation with high CTE and high modulus View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experimental characterization of transmission lines in thin-film multichip modules

    Page(s): 122 - 126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    Signal propagation on transmission lines fabricated in thin polyimide films on silicon substrates is investigated. Series resistive and shunt conductive losses are separated and it is shown that the effective dielectric loss is much higher than that expected from bulk material properties View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The evaluation of arc erosion on electrical contacts using three-dimensional surface profiles

    Page(s): 87 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1564 KB)  

    Three-dimensional surface profiling is a useful technique for the evaluation of electrical contact erosion. A review is given of the various methods by which a 3-D surface profile can be measured, and numerical techniques are described which can be used to analyze electrical contacts to define erosion in terms of volume and height changes. Experimental data on the rate of change of mass of Ag-CdO contacts are used to compare with volume and height changes over a number of switching cycles. Emphasis is given to the evaluation of 3-D surface profile in the particular condition where the change of mass of the contacts is nearly zero after a large number of break only switching cycles, and it is shown that in this condition the contacts exhibit volume changes both above and below the datum surface of a new contact View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Autocatalytic gold plating process for electronic packaging applications

    Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    An autocatalytic electroless gold process suitable for electronic packaging applications, particularly wirebonding needs, is described. This process yields high purity, nonporous soft gold of any thickness that meets or exceeds all military specifications. The process can be used for a wide variety of organic laminates (FR4, multifunctional epoxies), circuitized either subtractively or additively, in addition to ceramic substrates. A description of the process flow, bath parameters, bath performance, and resulting metallurgy will be described. The process acts as an excellent follow on to the conventional electroless nickel/immersion gold surface finishing systems currently practiced by the industry. Rate, purity, hardness, and wirebond data as a function of bath life (metal turnovers) will be discussed. The plating rate can be tuned between 1.5 and 2.5 μm/h. The resulting deposit remains pure (>99.93%) and soft (<70 knoop) even in the presence of metallic impurities and upon bath aging. Wirebond data as a function of gold thickness and plating parameters win also be presented. The process also has the ability to uniformly plate fine lines (>50 μm) separated by small spaces (>45 μm) without loss of line definition or bridging. The bath exhibits excellent throwing power. Drilled PTHs with aspect ratios as high as 15:1 (hole diameter of 0.03 mm, length of 0.45 mm) can be uniformly plated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Applicability and correction of temperature-voltage relation in the case of line contact

    Page(s): 113 - 121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    Contact temperature is one of the important factors in contact problems. The temperature-voltage relation is simple to use and applicable for temperature measurement in study, design, and use. In this relation, however, it is assumed that a contact has equivalent distributions between electric potential and temperature within it. If heat is transferred into the external atmosphere through the apparent contact surfaces and/or the contact faces, the relation may not be valid because of the disagreement between the two distributions. In this work, we take a line contact as an example and numerically analyze the effect of the heat transfer on the relation by using the finite difference method. The numerical computations are carried out using the values of electrical resistivity and thermal conductivity for Cu, which are assumed to be temperature-independent. The results show that the effect cannot be neglected under some conditions, We have also clarified the effect in terms of the correction factor, by which one cannot only establish the applicability of the relation, but also correct the theoretical values obtained from the relation. For this reason one can evaluate the effect without losing the simplicity and applicability of the relation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of solid-state intermetallic growth on the fracture toughness of Cu/63Sn-37Pb solder joints

    Page(s): 134 - 141
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2804 KB)  

    The mode I chevron notch fracture toughness of Cu/63Sn-37Pb solder joints was measured as a function of solid state copper-tin intermetallic growth at the solder/copper interface. Soldered chevron notched bend samples were aged in a furnace at 170°C to promote the intermetallic growth and the samples were tested at room temperature after 1, 3, 10, 30, and 75 days of growth. The total thickness of the interfacial intermetallic layer and the individual thicknesses of the component Cu6Sn5 and Cu3Sn layers were monitored at each stage. The chevron notch fracture toughness is correlated with the intermetallic layer thickness measurements and the fracture surface morphology. The results show that at a total intermetallic layer thickness below 5 μm, failure is dominated by microvoid coalescence in the solder, and intermetallic growth has little effect on the fracture toughness. At a total thickness exceeding 7 μm, however, fracture occurs by cleavage of the interfacial intermetallic particles and the fracture toughness decreases steadily as the intermetallic layer thickness increases. With a total intermetallic layer thickness of 19 μm, the chevron notch fracture toughness is only 30% of that measured for an as-soldered, nonaged solder joint View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Break arc duration and contact erosion in automotive application

    Page(s): 82 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    Switches and relays connected to complex circuits (motor, resistance, and lamp) and supplied by 14 V dc imposed by the battery voltage are currently used in the automobile field. Arc duration and subsequent erosion measurements for contacts made of pure silver, silver alloys (AgNi, AgCu), and silver metal-oxides (AgCdO, AgSnO2) were carried out. Also, the influence of the opening speed, current, and loads on this duration is determined. It was found that inductive load causes high voltage and gaseous arc phase development as was confirmed by spectra emission of surrounding gas N2. So, arc duration is enhanced but keeps the same values for silver alloys as well as for silver metal oxides. Nevertheless, in resistive and lamp loads, the metal oxide materials show large arc duration compared to pure silver or silver alloys. Opening speed acts on arc duration differently for each load: it decreases as root square of opening speed in the inductive load whatever the current, but follows a linear decrease at high current in the resistive case. The lowest erosion and mass transfer observed in resistive and lamps loads are reversed and enlarged when the load becomes inductive. We report the remarkable minimum erosion of AgSnO2 when loads are free from inductance. These results associated with measurements of erosion will be useful to choose contact material, electrical and mechanical conditions to improve lifetime and reliability of the components View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope