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IEEE Transactions on Computers

Issue 1 • Date Jan. 1996

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Displaying Results 1 - 13 of 13
  • Generalized Reed-Muller forms as a tool to detect symmetries

    Publication Year: 1996, Page(s):33 - 40
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (915 KB)

    In this paper, we present a new method for detecting groups of symmetric variables of completely specified Boolean functions. The canonical Generalized Reed-Muller (GRM) forms are used as a powerful analysis tool. To reduce the search space we have developed a set of signatures that allow us to identify quickly sets of potentially symmetric variables. Our approach allows for detecting symmetries o... View full abstract»

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  • Retiming-based partial scan

    Publication Year: 1996, Page(s):74 - 87
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1516 KB)

    A generally effective criterion for the selection of flip-flops in the partial scan problem for sequential circuit testability is to select flip-flops that break the cyclic structure of the circuit and reduce its sequential depth. The selection of flip-flops may also be subject to a prescribed bound on the clock period of the modified circuit (timing-driven partial scan). In this paper we propose ... View full abstract»

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  • Linear models for keystream generators

    Publication Year: 1996, Page(s):41 - 49
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    It is shown that an arbitrary binary keystream generator with M bits of memory can be linearly modeled as a non-autonomous linear feedback shift register of length at most M with an additive input sequence of nonbalanced identically distributed binary random variables. The sum of the squares of input correlation coefficients over all the linear models of any given length proves to be dependent on ... View full abstract»

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  • Utilization of on-line (concurrent) checkers during built-in self-test and vice versa

    Publication Year: 1996, Page(s):63 - 73
    Cited by:  Papers (9)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1048 KB)

    Concurrent checkers are commonly used in computer systems to detect computational errors on-line, which enhances reliability. Using the coding theory framework developed earlier by the authors, it is shown in the following that concurrent checkers, already available within the circuit, can be utilized very effectively during off-line testing. Specifically, test time as well as fault escape probabi... View full abstract»

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  • On the analysis and design of group theoretical t-syEC/AUED codes

    Publication Year: 1996, Page(s):103 - 108
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    An efficient algorithm to count the cardinalities of certain subsets of constant weight binary vectors is presented in this paper. The algorithm enables us to design I-symmetric error correcting/all unidirectional error detecting (1-syEC/AUED) codes with the highest cardinality based on the group Zn. Since a field Zp is a group, this algorithm can also be used to design a fie... View full abstract»

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  • Analysis of periodic and intermediate boundary 90/150 cellular automata

    Publication Year: 1996, Page(s):1 - 12
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1052 KB)

    Considerable interest has been recently generated in the study of Cellular Automata (CA) behavior. Polynomial and matrix algebraic tools are employed to characterize some of the properties of null/periodic boundary CA. Some other results of group CA behavior have been reported based on simulation studies. This paper reports a formal proof for the conjecture-there exists no primitive characteristic... View full abstract»

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  • Test generation with dynamic probe points in high observability testing environment

    Publication Year: 1996, Page(s):88 - 96
    Cited by:  Papers (1)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    High observability testing environment allows internal circuit nodes to be used as test points. However, such flexibility requires the development of new ATPG algorithm. Previous reported algorithm does not guarantee full fault-coverage and assumes all internal circuit nodes are test points. The new algorithm described in this paper will generate a full fault-coverage test set for a fanout free co... View full abstract»

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  • On the number of tests to detect all path delay faults in combinational logic circuits

    Publication Year: 1996, Page(s):50 - 62
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1296 KB)

    The problems involved in handling large numbers of path delay faults were alleviated in previous works, by developing fault simulation and test generation procedures that do not require paths to be explicitly considered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. With the problems related to the number of paths rem... View full abstract»

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  • Generation of minimal vertex covers for row/column allocation in self-repairable arrays

    Publication Year: 1996, Page(s):109 - 115
    Cited by:  Papers (14)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    This paper lays foundations for an approach to on-chip row/column allocation that exploits certain properties offered by laterally connected networks of simple threshold devices. As a sample application, it is demonstrated how electronic implementations of these networks can be used as the basis for effective memory array repair systems that require little hardware overhead View full abstract»

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  • A new residue arithmetic error correction scheme

    Publication Year: 1996, Page(s):13 - 19
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    Automatic detection and correction of errors in the residue number system involves the conversion of residue representations to integers and base extension. The residue number system is generally restricted to moduli that are pairwise relatively prime. In this paper we consider error detection and correction using a moduli set with common factors. A method to construct a moduli set that leads to s... View full abstract»

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  • Optimally routing LC permutations on k-extra-stage cube-type networks

    Publication Year: 1996, Page(s):97 - 103
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    It is difficult to partition an arbitrary permutation into a minimum number of groups such that conflict-free paths for all source-destination pairs in each group can be established on an omega network. Based on linear algebra theory, this paper presents an optimal algorithm which solves this problem for the LC class of permutations on a large class of multi-stage networks. This algorithm extends ... View full abstract»

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  • Hyperneural network-an efficient model for test generation in digital circuits

    Publication Year: 1996, Page(s):115 - 121
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    This paper considers the problem of applying neural network for logic circuit testing and proposes an efficient method based on hyperneural network (HNN). The HNN uses an energy function that not only considers binary relations but also captures all higher order relations among N neurons. We illustrate the hyperneural concept using two formulations. First, a constraint energy function is defined a... View full abstract»

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  • On removing redundancies from synchronous sequential circuits with synchronizing sequences

    Publication Year: 1996, Page(s):20 - 32
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1376 KB)

    We consider the removal of redundant logic from synchronous sequential circuits that have synchronizing sequences. The logic to be removed is identified by determining line stuck-at faults that do not affect the operation of the circuit. Such signal lines and some of the logic surrounding them can be removed without affecting the operation of the circuit. We show that circuits that have synchroniz... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org