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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1996

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Displaying Results 1 - 13 of 13
  • Generalized Reed-Muller forms as a tool to detect symmetries

    Page(s): 33 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (915 KB)  

    In this paper, we present a new method for detecting groups of symmetric variables of completely specified Boolean functions. The canonical Generalized Reed-Muller (GRM) forms are used as a powerful analysis tool. To reduce the search space we have developed a set of signatures that allow us to identify quickly sets of potentially symmetric variables. Our approach allows for detecting symmetries of any number of inputs simultaneously. Totally symmetric functions can be detected very quickly. The traditional definitions of symmetry have also been extended to include more types. This extension has the advantage of grouping input variables into more classes. Experiments have been performed on MCNC benchmark cases and the results verify the efficiency of our method. View full abstract»

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  • Test generation with dynamic probe points in high observability testing environment

    Page(s): 88 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    High observability testing environment allows internal circuit nodes to be used as test points. However, such flexibility requires the development of new ATPG algorithm. Previous reported algorithm does not guarantee full fault-coverage and assumes all internal circuit nodes are test points. The new algorithm described in this paper will generate a full fault-coverage test set for a fanout free combinational circuit. The main characteristic of the algorithm is that it generates test vectors as well as probe points. As a result, the probe points are different for each test vector, and the number of probe points is the minimum for test set generated. Results obtained show that an average of 30% test vector reduction is achieved compared with the conventional test method which uses only output pins as test points View full abstract»

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  • On removing redundancies from synchronous sequential circuits with synchronizing sequences

    Page(s): 20 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB)  

    We consider the removal of redundant logic from synchronous sequential circuits that have synchronizing sequences. The logic to be removed is identified by determining line stuck-at faults that do not affect the operation of the circuit. Such signal lines and some of the logic surrounding them can be removed without affecting the operation of the circuit. We show that circuits that have synchronizing sequences have certain properties that help in identifying logic that can be removed. Specifically, their state diagrams have a strongly connected component that contains all the synchronization states. This strongly connected component, called the main strongly-connected component, is reachable from all other strongly connected components. In addition to redundant faults that can always be removed, we show that there are two types of partially detectable faults in circuits that have synchronizing sequences. In the presence of the first type of faults, the circuit becomes unsynchronizable. Signal lines carrying such faults cannot be removed. The other type of partially detectable faults leave the circuit synchronizable. We show that such faults do not affect the main strongly connected component, and hence the corresponding signal lines can be removed without affecting the operation of the circuit after it is synchronized. We also define weakly synchronizable circuits acid derive similar results regarding the removal of redundant logic in them. The class of removable lines is thus extended beyond those corresponding to redundant faults to include some partially detectable faults as well. We present experimental evidence to the existence of partially detectable faults that correspond to signal lines that can be removed in benchmark circuits View full abstract»

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  • Analysis of periodic and intermediate boundary 90/150 cellular automata

    Page(s): 1 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1052 KB)  

    Considerable interest has been recently generated in the study of Cellular Automata (CA) behavior. Polynomial and matrix algebraic tools are employed to characterize some of the properties of null/periodic boundary CA. Some other results of group CA behavior have been reported based on simulation studies. This paper reports a formal proof for the conjecture-there exists no primitive characteristic polynomial of 90/150 CA with periodic boundary condition. For generation of high quality pseudorandom patterns, it is necessary to employ CA having primitive characteristic polynomial. There exist two null boundary CA for every primitive polynomial. However, for such Cs the quality of pseudorandomness suffers in general, particularly in the regions around the terminal cells because of null boundary condition. In this background, a new concept of intermediate boundary CA has been proposed to generate pseudorandom patterns that are better in quality than those generated with null boundary CA. Some interesting properties of intermediate boundary CA are also reported View full abstract»

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  • Hyperneural network-an efficient model for test generation in digital circuits

    Page(s): 115 - 121
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    This paper considers the problem of applying neural network for logic circuit testing and proposes an efficient method based on hyperneural network (HNN). The HNN uses an energy function that not only considers binary relations but also captures all higher order relations among N neurons. We illustrate the hyperneural concept using two formulations. First, a constraint energy function is defined and the gate model is obtained. Second, the Hopfield network is reformulated to generate the gate level hyperneural model. The gate level HNN are used to give a mathematical form to the digital circuit that, in turn, requires optimization techniques to solve the test generation problem. We have used ISCAS'85 benchmark circuits to illustrate the method. Results are compared with those obtained from PODEM, MODEM, and FAN View full abstract»

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  • Optimally routing LC permutations on k-extra-stage cube-type networks

    Page(s): 97 - 103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    It is difficult to partition an arbitrary permutation into a minimum number of groups such that conflict-free paths for all source-destination pairs in each group can be established on an omega network. Based on linear algebra theory, this paper presents an optimal algorithm which solves this problem for the LC class of permutations on a large class of multi-stage networks. This algorithm extends the previous result which deals with the BPC class of permutations on the omega network View full abstract»

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  • On the analysis and design of group theoretical t-syEC/AUED codes

    Page(s): 103 - 108
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    An efficient algorithm to count the cardinalities of certain subsets of constant weight binary vectors is presented in this paper. The algorithm enables us to design I-symmetric error correcting/all unidirectional error detecting (1-syEC/AUED) codes with the highest cardinality based on the group Zn. Since a field Zp is a group, this algorithm can also be used to design a field 1-syEC/AUED code. We can construct t-syEC/AUED codes for f=2 or 3 by appending a tail to the field 1-syEC/AUED codes. The information rates of the proposed t-syEC/AUED codes are shown to be better than the previously developed codes View full abstract»

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  • Linear models for keystream generators

    Page(s): 41 - 49
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    It is shown that an arbitrary binary keystream generator with M bits of memory can be linearly modeled as a non-autonomous linear feedback shift register of length at most M with an additive input sequence of nonbalanced identically distributed binary random variables. The sum of the squares of input correlation coefficients over all the linear models of any given length proves to be dependent on a keystream generator. The minimum and maximum values of the correlation sum along with the necessary and sufficient conditions for them to be achieved are established. An effective method for the linear model determination based on the linear sequential circuit approximation of autonomous finite-state machines is developed. Linear models for clock controlled shift registers and arbitrary shift register based keystream generators are derived. Several examples including the basic summation generator, the clock-controlled cascade, and the shrinking generator are presented. Linear models are the basis for a general structure-dependent and initial-state-independent statistical test. They may also be used for divide and conquer correlation attacks on the initial state. Security against the corresponding statistical attack appears hard to control in practice and generally hard to achieve with simple keystream generator schemes View full abstract»

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  • Retiming-based partial scan

    Page(s): 74 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1516 KB)  

    A generally effective criterion for the selection of flip-flops in the partial scan problem for sequential circuit testability is to select flip-flops that break the cyclic structure of the circuit and reduce its sequential depth. The selection of flip-flops may also be subject to a prescribed bound on the clock period of the modified circuit (timing-driven partial scan). In this paper we propose two techniques (for non-timing-driven and timing-driven partial scan) which address the above criterion based on a transformation of sequential circuits known as retiming. For non-timing-driven partial scan, we employ retiming to rearrange the flip-flops of the circuit, so that its functionality is preserved, while the number of flip-flops that are needed to break all cycles and bound the sequential depth is significantly reduced. For timing-driven partial scan, we propose a retiming-based technique that reduces the overall area overhead required to achieve the clock period bound. Experimental results on the ISCAS'89 circuits show the benefit of our approach in both timing-driven and non-timing-driven partial scan View full abstract»

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  • A new residue arithmetic error correction scheme

    Page(s): 13 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    Automatic detection and correction of errors in the residue number system involves the conversion of residue representations to integers and base extension. The residue number system is generally restricted to moduli that are pairwise relatively prime. In this paper we consider error detection and correction using a moduli set with common factors. A method to construct a moduli set that leads to simplified error detection and correction is presented. Error detection can now be performed by computing residues in parallel. Error correction does not involve base extension any more. It is also shown that, removing all restrictions on the moduli set, leads to more complex error detection/correction algorithms View full abstract»

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  • Utilization of on-line (concurrent) checkers during built-in self-test and vice versa

    Page(s): 63 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    Concurrent checkers are commonly used in computer systems to detect computational errors on-line, which enhances reliability. Using the coding theory framework developed earlier by the authors, it is shown in the following that concurrent checkers, already available within the circuit, can be utilized very effectively during off-line testing. Specifically, test time as well as fault escape probability can both be reduced simultaneously. The proposed combined scheme can be implemented with simple modification of existing hardware. Also shown is a novel use of BIST hardware for concurrent checking. Specifically proposed is a novel, dual use of concurrent checkers and built-in self-test hardware, yielding mutual advantage View full abstract»

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  • Generation of minimal vertex covers for row/column allocation in self-repairable arrays

    Page(s): 109 - 115
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    This paper lays foundations for an approach to on-chip row/column allocation that exploits certain properties offered by laterally connected networks of simple threshold devices. As a sample application, it is demonstrated how electronic implementations of these networks can be used as the basis for effective memory array repair systems that require little hardware overhead View full abstract»

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  • On the number of tests to detect all path delay faults in combinational logic circuits

    Page(s): 50 - 62
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    The problems involved in handling large numbers of path delay faults were alleviated in previous works, by developing fault simulation and test generation procedures that do not require paths to be explicitly considered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. With the problems related to the number of paths removed, a new limiting factor in test generation for path delay faults is revealed, namely, the number of tests required to detect all path delay faults. In this work, the problems related to the number of tests are investigated. A procedure for computing a lower bound on the number of tests is described, and methods for synthesizing circuits with reduced lower bounds on the numbers of tests are developed. Experimental results are presented to demonstrate various aspects of the problem View full abstract»

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albert.zomaya@sydney.edu.au