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Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on

Issue 4 • Date Dec. 1995

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Displaying Results 1 - 18 of 18
  • A methodology for laser-based thermal diffusivity measurement of advanced multichip module ceramic materials

    Publication Year: 1995 , Page(s): 773 - 780
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (957 KB)  

    Alumina derivative ceramics and low temperature co-fired ceramic (LTCC) electronic multichip module (MCM) packaging substrates have been characterized using single- and double-sided inspection laser flash thermal diffusivity measurement techniques. The paper highlights problems associated with both the measurement system and associated data analysis for the single-sided measurement, and these data are evaluated with reference to that measured by an existing (double sided inspection) standard laser flash method. Finally, a preliminary single-sided measurement methodology is proposed. View full abstract»

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  • Correction to "A Simple Test Chip to Assess Chip and Package Design in the Case of Plastic Assemblin

    Publication Year: 1995
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (203 KB)  

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  • Thermal characterization of electronic devices with boundary condition independent compact models

    Publication Year: 1995 , Page(s): 723 - 731
    Cited by:  Papers (33)  |  Patents (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    The accurate prediction of operating temperatures of temperature-sensitive electronic parts at the component-, board-, and system-level is seriously hampered by the tack of reliable, standardized input data. The situation which prevails today is that component manufacturers supply to end users experimental data which characterizes the thermal behavior of packages under a set of standardized and idealized conditions. Such characterizations normally involve the junction-to-case thermal resistance or the junction-to-ambient resistance according to MIL or SEMI standards. There are several practical difficulties associated with such an approach, which will be shortly commented upon. Today, the need for more accurate junction temperature prediction becomes increasingly urgent, and the call for a precise definition of the various thermal resistances is heard by a growing number of researchers. An earlier paper discussed the pros and cons of several methods that describe the thermal behavior of electronic parts. It was concluded that none of these methods is capable of meeting the objectives that are proposed. In this paper, a novel approach is introduced, based on the derivation of a simple resistance network starting from a detailed model, using optimization techniques. The proposed method is applied to two cases:a so-called “validation” chip, functioning as a benchmark for the software that is used to generate the detailed model; and a 208-PQFP component. It is demonstrated that it is possible to create a compact model comprising a simple resistance network, representing the detailed model to a high accuracy, which is independent of the boundary conditions View full abstract»

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  • High performance forced air cooling scheme employing microchannel heat exchangers

    Publication Year: 1995 , Page(s): 795 - 804
    Cited by:  Papers (16)  |  Patents (54)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1244 KB)  

    In this paper, a high performance forced air cooing scheme is theoretically and experimentally investigated which employs microchannel parallel plate-fin heat sinks and tubes to deliver the air to and optionally from the heat sink. The performance of the cooling system is modeled in terms of thermal resistance, pressure drop, and pumping power. Optimizations are performed and design trade-offs discussed. Tubes are observed to have a significant impact on optimum heat sink design as well as operating point. Sample heat sinks with lateral dimensions of 5×5 cm2 and fin lengths of 1.5 and 2.5 cm were fabricated from copper and aluminum foils using a simple assembly process. Fin thicknesses and channel widths of the heat sinks are on the order of 200 and 500 μm, respectively. Thermal resistances as low as 0.2 R/W are measured. Results of the present study are compared to prior works dealing with direct air cooling. The thermal performances achievable using the investigated cooling approach are superior to those attainable using open air cooled heat sinks as well as those employing silicon microcoolers View full abstract»

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  • Methodology for thermal evaluation of multichip modules

    Publication Year: 1995 , Page(s): 758 - 764
    Cited by:  Papers (5)  |  Patents (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    Multichip modules provide shorter interconnection lengths between the chips, higher speeds and lower costs. This higher system performance is the driving force for advances in MCM packaging technology. A potential limitation is the ability to remove heat from these packages. With higher chip densities, the thermal management of multichip modules poses a real challenge to the package manufacturer. There is a need to define the junction-to-ambient and junction-to-case thermal resistances for multichip modules in a more rigorous manner while reducing the number of thermal tests needed to evaluate an MCM and provide information to predict junction temperatures under arbitrary powering up of the individual dice. For high reliability, it is critical that maximum specified operating junction temperatures are not exceeded. Experiments were performed for nonuniform powering up of an MCM mounted on a vertical board in natural and forced convection. The package tested was a 208-lead Amkor PMCM. The average chip temperature due to multiple sources within the module was considered as the reference temperature for evaluating the junction temperature rise of the particular chip. The concept of superposition of temperatures was found to capture the effect of the background heating of the chip due to its neighbors as well as the individual power dissipation from the chip in question. This approach offers a more refined methodology for evaluation of nonuniformly powered multichip modules compared to previous methods View full abstract»

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  • Experimental investigation of subcooled liquid nitrogen impingement cooling of a silicon chip

    Publication Year: 1995 , Page(s): 788 - 794
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    A technique was developed to facilitate subcooled pool boiling and jet impingement boiling of liquid nitrogen at the surface of a silicon chip by varying the dewar pressure while maintaining the bath temperature constant at about 78 K. Subcooling levels of up to 10 K could be easily reached by pressurizing the liquid nitrogen bath with helium gas. Convective and boiling impingement cooling of up to 80 W/cm 3 from a silicon chip has been measured for a submerged subcooled liquid nitrogen jet View full abstract»

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  • The evolution of IBM high performance cooling technology

    Publication Year: 1995 , Page(s): 805 - 811
    Cited by:  Papers (4)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    This paper provides a perspective and review of the evolution of high performance cooling technology that has been developed and used in IBM medium and large-scale computers over the past 25 years. Package cooling technology and its evolution, leading to the development of the thermal conduction module (TCM) is described. The development of air cooling technology is discussed; along with enhancements using turbulators, air-to liquid heat exchangers, and impinging flow. The development of water cooling and direct liquid immersion technology is also covered View full abstract»

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  • Achieving accurate thermal characterization using a CFD code-case study of plastic packages

    Publication Year: 1995 , Page(s): 732 - 738
    Cited by:  Papers (5)  |  Patents (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    Achieving component-level thermal characterization using computational fluid dynamics (CFD) is assessed using a case study approach. A commercial CFD code (FLOTHERM) is used to simulate the thermal performance of three plastic-based microelectronic packages (68-lead and 84-lead plastic leaded chip carriers or PLCC's, and a 164-lead plastic quad flat pack or PQFP) under forced air cooling conditions. Predictions of junction-to-ambient thermal resistance (θja) are compared to experimental measurements. One aspect of the work is to use results from a single situation (84-PLCC and an approach air velocity of 1.52 m/s) to develop a set of “modeling guidelines”. These modeling guidelines are then applied to the other components (68-PLCC and 164-PQFP) and flow conditions (0.7-3.05 m/s) to test their validity. Guideline parameters include near component flow field nodalization, geometric detail in representing conduction paths and code user options such as turbulent flow models. The average deviation of predicted versus measured values of θja was 7.5% using the derived guidelines. An additional component design sensitivity investigated was the effect of the introduction of a heat spreading “heat post” in the high temperature regions of the 164-PQFP, View full abstract»

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  • Fine line thin dielectric circuit board characterization

    Publication Year: 1995 , Page(s): 842 - 850
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB)  

    The rough surface of the copper foil, introduced to enhance its interfacial adhesion to the dielectric medium, will increase the signal propagation time constant and reduce the characteristic impedance of a signal line. The influence increases as the dielectric thickness decreases. Two high resolution resonant measurement techniques will be presented for such studies. The additional delay term due to the internal inductance at the frequency of interest is proportional to the square root of the signal rise time in the transient measurement. The additional delay associated with the signal rise time degradation due to skin effect resistance loss is minimized by measuring the delay at 1% of the voltage swing. We will also compare the results of different measurement techniques in this paper View full abstract»

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  • Development of an inspection process for ball-grid-array technology using scanned-beam X-ray laminography

    Publication Year: 1995 , Page(s): 851 - 861
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1648 KB)  

    An inspection process based on scanned-beam X-ray laminography (SBXLAM) is proposed herein for quantitatively monitoring the quality of ball-grid-array (BGA) joints. The long-term reliability of the BGA joints depends on the component-assembly process producing joints with sufficient solder volume and proper alignment. Inspection algorithms were developed to measure the critical BGA-joint characteristics, including the alignment between the ball and the PCB pad, the solder thickness, and the average joint-diameter, and thus, determine whether the joints are defective. The performance of the inspection algorithms was evaluated by inspecting samples with defects that were independently verified View full abstract»

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  • Analysis of a thermally enhanced ball grid array package

    Publication Year: 1995 , Page(s): 749 - 757
    Cited by:  Papers (17)  |  Patents (46)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    A thermally enhanced ball grid array package (SuperBGA package) has been developed. Its thermal performance has been analyzed using a nonlinear, lumped parameter model. This model uses a temperature-dependent heat transfer coefficient which accounts for the natural, mixed, and forced convection regimes and radiative heat transfer. The accuracy of the model is verified experimentally using one package size. The model is then used to predict the thermal performance of other package sizes and to rationalize the high level of thermal performance exhibited by the package View full abstract»

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  • Optimum design and selection of heat sinks

    Publication Year: 1995 , Page(s): 812 - 817
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    An analytical simulation model has been developed for predicting and optimizing the thermal performance of bidirectional fin heat sinks in a partially confined configuration. Sample calculations are carried out, and parametric plots are provided, illustrating the effect of various design parameters on the performance of a heat sink. It is observed that the actual convection flow velocity through fins is usually unknown to designers, yet, is one of the parameters that greatly affect the overall thermal performance of a heat sink. In this paper, a simple method of determining the fin flow velocity is presented, and the development of the overall thermal model is described. An overview of different types of heat sinks and associated design parameters is provided. Optimization of heat-sink designs and typical parametric behaviors are discussed based on the sample simulation results View full abstract»

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  • Asymptotic thermal analysis of electronic packages and printed-circuit boards

    Publication Year: 1995 , Page(s): 781 - 787
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    The electric thermal network analogy method is widely used to study thermal behavior of electronic components. This analogy usually leads to a large resistance-capacitance (RC) network. Conventional simulation techniques of these networks require substantial computational resources. This paper presents a new solution technique based on a recently developed asymptotic waveform evaluation (AWE) concept which has been successfully used for transient simulation of large electrical networks. Application of AWE to time dependent thermal analysis of printed circuit boards often results in two orders of magnitude speed-up over current iterative techniques, yet retaining comparable accuracy View full abstract»

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  • Degradation of gold-aluminium ball bonds by aging and contamination

    Publication Year: 1995 , Page(s): 835 - 841
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB)  

    The degradation of gold aluminium ball bonds has been studied by shear tests, resistivity measurements, micrographs, EDX and AES as a function of aging time at elevated temperatures and after various contamination treatments before and after bonding. Samples were subjected to ion etching treatment immediately before bonding in order to guarantee a comparable initial state. Incorporation of large amounts of Cl, Br, and F into the surface layer of the pad and other contamination treatments before bonding did not show detectable effects in subsequent annealing treatments as long as the bonding process itself has not been impeded by thick surface layers. The degradation process during annealing can be described as a three stage mechanism. Each stage can be clearly distinguished by the fracture behavior in the shear test, the morphology of the bond shown by the micrographs and by the change of contact resistivity View full abstract»

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  • Substrate temperatures of liquid nitrogen cooled multichip modules utilizing wirebonded die

    Publication Year: 1995 , Page(s): 827 - 834
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    Substrate temperatures for liquid nitrogen cooled MCM assemblies utilizing wire-bonded chips were investigated to determine the thermal limits for using superconducting chip-to-chip interconnects. A boiling curve was obtained for this configuration from Sandia's ATC-03 assembly test chips using integral surface resistance heaters and diode thermometers which indicated that 23 W/cm2 could be dissipated by nucleate boiling before the onset of film boiling at 90 K, 13°C above nitrogen's 77 K boiling point at atmospheric pressure. This measured boiling curve was incorporated into a finite-element model of an array of face-up 1 cm2 silicon chips on an MgO substrate and used to predict the temperature on the surface of the interconnecting substrate as a function of chip power dissipation, distribution of the powered area on the chip, and chip separation. ICs on such an MCM should not be operated in the film boiling regime because temperature fluctuations peaking as high as 118 K could propagate from the upper surface of the chips, through the silicon and die attach material and down to the superconducting interconnects. Therefore the onset of film boiling anywhere on the assembly represents an upper limit of power dissipation for the system. 1 cm2 chips separated by 2 mm could dissipate 30 W each before film boiling began in the middle of the top of the chips resulting in a maximum substrate temperature of 89.8 K directly under that spot. Since film boiling in this closest-packed configuration begins at a temperature in the vicinity of Tc for YBCO systems, decreasing critical current density may limit the operating temperature of these interconnects before the onset of film boiling on the chips. Superconductors based on thallium or mercury have sufficient headroom to avoid this further limitation View full abstract»

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  • Heat-transfer engineering in systems integration: outlook for closer coupling of thermal and electrical designs of computers

    Publication Year: 1995 , Page(s): 818 - 826
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1232 KB)  

    This paper begins with a review of the author's personal experience in the research field of computer cooling. It highlights the need to develop foresight on the possible course of hardware development in order to provide the package designer with appropriate heat-transfer data in a timely manner. A question is then raised about the immediate future of the (indirect) water-cooling technology. Water-cooling has so far proven effective in cooling high-end computers which use ECL devices in two-dimensional packaging. The drive toward higher raw speeds of ECL devices, however, is going to lose steam-emerging instead is the endeavor to upgrade system performance by massively-parallel computing which requires wiring-intensive hardware. Three-dimensional packaging will meet the demand for short global wiring in systems, but will become a commercial reality only after the establishment of methodologies for its design and assembling. One of the key issues in the design of 3-D computers is the optimum allocation of physical space for electrical wiring and heat-transfer paths. Intimate coupling of wiring and heat transfer designs pose challenges to heat-transfer researchers that have not surfaced in other industrial applications. Items of primary importance include: the methodology to predict how and temperature distributions in a field having a wide spectrum of length scales, the local heat-transfer coefficients in the maze of microscale coolant channels, the possibly large effect of extraneous factors such as irregular geometric features of coolant channels and conjugate mode of heat transfer, and temperature control during assembling of 3-D structures View full abstract»

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  • An assessment of the thermal performance of the PBGA family

    Publication Year: 1995 , Page(s): 739 - 748
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB)  

    The plastic ball grid array (PBGA) has generated significant interest as a cost effective packaging alternative for high I/O ULSI devices. This study assesses thermal performance of the PBGA family using the metric of power dissipation capability-“power rating” for IC packages. The metric chosen is the power dissipated for constraints of junction temperature (<105°C), and board temperature (<90°C), in low aspect ratio enclosures (portable products), as well as natural and forced air convection (~1.0 m/s) equipment operating conditions. The free and forced air conditions are typical of PC/workstation environments. Simulation studies using a finite difference based software for thermal performance of IC packages investigated the relative roles of package enhancements toward the thermal performance. Experimental data for the 106 PBGA in free air and portable radio mockup, and the 119 PBGA in free and forced air were used to validate the methodology. The study covers 68-324 pincount PBGAs and compares the performance with comparable pincount PQFPs (plastic quad hat package) and other contemporary package styles. The study also addresses system level enhancements for extending the thermal performance of PBGAs for applications View full abstract»

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  • Thermal characterization of vertical multichip modules MCM-V

    Publication Year: 1995 , Page(s): 765 - 772
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB)  

    This paper describes the thermal characterization of a vertical multichip module (MCM-V) technology. The MCM-V technology encloses a stack of IC's in a three dimensional cube of plastic molding compound, with the inter-chip electrical connections made on the outside faces of the tube. Thermal measurements mere carried out on two different sized modules containing eight specially designed package evaluation test chips. Steady state and transient thermal results are presented. Simulation results are shown for two applications manufactured using the MCM-V technology; a 2 W, 16 chip 256 MBit DRAM module and a 3 W: 9 chip image processing system View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope