IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 2 • Feb. 2007

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  • Table of contents

    Publication Year: 2007, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2007, Page(s): C2
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  • Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper

    Publication Year: 2007, Page(s):125 - 134
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1887 KB) | HTML iconHTML

    In this paper, efficient clock delayed domino logic with variable strength voltage keeper is proposed. The variable strength of the keeper is achieved through applying two different body biases to the keeper. The circuits used to generate the body biases are called capacitive body bias generator and cross-coupled capacitive body bias generator. Compared to a previous work, the body bias generator ... View full abstract»

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  • Design Methodology for Global Resonant H-Tree Clock Distribution Networks

    Publication Year: 2007, Page(s):135 - 148
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1471 KB) | HTML iconHTML

    Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described, supporting the design of low power, skew, and jitter resonant H-tree clock distribution networks. Excellent agreement is shown between the proposed model and SpectraS simulations. A case study is presented that demonstrates the de... View full abstract»

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  • Integrated Placement and Skew Optimization for Rotary Clocking

    Publication Year: 2007, Page(s):149 - 158
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (673 KB) | HTML iconHTML

    The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have started playing an increasingly important role in limiting the performance of the clock network. Rotary clocking is a novel technique which employs unterminated rings formed by differential transmission lines to save power an... View full abstract»

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  • Interconnect Lifetime Prediction for Reliability-Aware Systems

    Publication Year: 2007, Page(s):159 - 172
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1242 KB) | HTML iconHTML

    Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature dependence of leakage power, circuit performance, IC package cost, and reliability. While many interconnect reliability models assume a constant temperature, this paper analyzes the effects of temporal and spatial thermal gradients on interconnect lifetime in terms of electromigration, a... View full abstract»

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  • A New Single-Ended SRAM Cell With Write-Assist

    Publication Year: 2007, Page(s):173 - 181
    Cited by:  Papers (13)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (533 KB) | HTML iconHTML

    A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is presented. The WA technique reduces the problem of writing a "one" through an nMOS pass device, thereby making a single-ended bit line more attractive. Both active power and leakage power can be significantly reduced. Leakage charge can be pooled to help precharge bit lines. Cell area and performance are competiti... View full abstract»

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  • Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs

    Publication Year: 2007, Page(s):182 - 195
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1286 KB) | HTML iconHTML

    This article introduces a novel lookup table (LUT) and its usage in the configurable logic block (CLB) architectures for SRAM-based field-programmable gate array (FPGA) architectures. The proposed CLB allows sharing of SRAM tables of LUTs among NPN-equivalent functions to reduce the size of memories used for storing the functions and also reduces the number of configuration bits required. We measu... View full abstract»

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  • Segmented Virtual Ground Architecture for Low-Power Embedded SRAM

    Publication Year: 2007, Page(s):196 - 205
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1089 KB) | HTML iconHTML

    A new scheme to reduce the power consumption of static random access memories is presented. It is shown that using segmented virtual grounding (SVGND), it is possible to reduce both dynamic and static power consumption. The leakage power of the cells is reduced by reducing the voltage drop over a cell. The dynamic power dissipation is also reduced by eliminating the power consumption due to the di... View full abstract»

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  • A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations

    Publication Year: 2007, Page(s):206 - 215
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB) | HTML iconHTML

    The impact of parameter variations on timing due to process variations has become significant in recent years. In this paper, we present a statistical timing analysis (STA) framework with quadratic gate delay models that also captures spatial correlations. Our technique does not make any assumption about the distribution of the parameter variations, gate delays, and arrival times. We propose a Tay... View full abstract»

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  • Online Fault Tolerance for FPGA Logic Blocks

    Publication Year: 2007, Page(s):216 - 226
    Cited by:  Papers (43)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (964 KB) | HTML iconHTML

    Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for F... View full abstract»

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  • A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

    Publication Year: 2007, Page(s):227 - 231
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (601 KB) | HTML iconHTML

    A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer wit... View full abstract»

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  • Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses

    Publication Year: 2007, Page(s):231 - 236
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2445 KB) | HTML iconHTML

    This paper demonstrates that driver preemphasis technique can be used for on-chip global buses to increase signal channel bandwidth. Compared to conventional repeater insertion techniques, driver preemphasis saves repeater layout complexity and reduces power consumption by 12%-39% for data activity factors above 0.1. A driver circuit architecture using voltage-mode preemphasis technique was tested... View full abstract»

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  • Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs

    Publication Year: 2007, Page(s):236 - 240
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (795 KB) | HTML iconHTML

    Traditional approaches of automatic gain control (AGC) involve estimating the average power or the peak amplitude over an extended time period, which results in high hardware complexity and a long processing time. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference. In this paper, we propose a joint AGC and equalization (Joint AGC-EQ) scheme... View full abstract»

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  • Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes

    Publication Year: 2007, Page(s):240 - 245
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (853 KB) | HTML iconHTML

    This paper presents a stochastic approach for bus arbiter design. Arbiter design includes policy design, buffer insertion, and optimal buffer sizing. The methodology uses continuous-time Markov decision processes (CTMDPs) to get optimal arbitration policies and buffer space distribution. The mathematical formulation of this problem in terms of a CTMDP framework leads to a linear programming proble... View full abstract»

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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Publication Year: 2007, Page(s): 246
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  • Order form for reprints

    Publication Year: 2007, Page(s): 247
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2007, Page(s): 248
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2007, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2007, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu