IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 1 • Jan. 2007

Filter Results

Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2007, Page(s): C1
    Request permission for commercial reuse | PDF file iconPDF (39 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2007, Page(s): C2
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • A Reflection on the TVLSI Editorial Process and the Announcement of a New Editor-In-Chief

    Publication Year: 2007, Page(s):1 - 4
    Request permission for commercial reuse | PDF file iconPDF (517 KB) | HTML iconHTML
    Freely Available from IEEE
  • Low-Power Rotary Clock Array Design

    Publication Year: 2007, Page(s):5 - 12
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (542 KB) | HTML iconHTML

    Rotary clock is a recently proposed clock distribution technique based on wave propagation in transmission lines. In this paper, we investigate the problem of power minimization of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit that is capable of extracting the SPICE netlist from the layout specification of a rotary c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Two New Techniques Integrated for Energy-Efficient TLB Design

    Publication Year: 2007, Page(s):13 - 23
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1727 KB) | HTML iconHTML

    The translation lookaside buffer (TLB) is an essential component used to speed up the virtual-to-physical address translation. Due to frequent lookup, however, the power consumption of the TLB is usually considerable. This paper presents an energy-efficient TLB design for the embedded processors. In our design, we first propose a real-time filter scheme to facilitate the block buffering to elimina... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Test Generation Framework for Quantum Cellular Automata Circuits

    Publication Year: 2007, Page(s):24 - 36
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1559 KB) | HTML iconHTML

    In this paper, we present a test generation framework for quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted recent significant attention and shows promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to g... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup

    Publication Year: 2007, Page(s):37 - 47
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (983 KB) | HTML iconHTML

    The increasing share of test and packaging as a percentage of the overall cost for RF transceivers necessitate, radically test new approaches to both wafer-level and final production testing. We present a new system-level test setup for voltage-controlled oscillator (VCO) modulating transceiver architectures that we call the delayed-RF setup, along with a novel, all-digital design-for-testability ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels

    Publication Year: 2007, Page(s):48 - 59
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB) | HTML iconHTML

    With the ever increasing signal speeds, signal integrity issues of high-speed VLSI designs are presenting increasingly difficult challenges for state-of-the-art modeling and simulation tools. Consequently, characterization and passive macromodeling of high-speed modules such as interconnects, vias, and packages based on tabulated data are becoming important. This paper presents a fast algorithm fo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm

    Publication Year: 2007, Page(s):60 - 68
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1524 KB) | HTML iconHTML

    The partial element equivalent circuit (PEEC) approach has been used in different forms for the computation of equivalent circuit elements for quasi-static and full-wave electromagnetic models. In this paper, we focus on the topic of large scale inductance computations. For many problems as part of PEEC modeling, partial inductances need to be computed to model interactions between a large numbers... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

    Publication Year: 2007, Page(s):69 - 79
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1151 KB) | HTML iconHTML

    A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus architecture, multiple compatible bus transactions can be performed simultaneously with only a single bus access grant from the bus arbiter. Experimental results show that, compared with a traditional bus architecture, the SAMBA-bus architecture can have up to 3.5 times improvement in the effective ba... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design

    Publication Year: 2007, Page(s):80 - 89
    Cited by:  Papers (30)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB) | HTML iconHTML

    The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in wrong values being latched in the circuit registers. We propose a design methodology for limiting the maximum value of the supply/ground currents to a user-specified threshold level while minimizing the wake up (sleep to a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends

    Publication Year: 2007, Page(s):90 - 103
    Cited by:  Papers (68)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB) | HTML iconHTML

    As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital part. In this paper, first, a system level ene... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

    Publication Year: 2007, Page(s):104 - 114
    Cited by:  Papers (77)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1366 KB) | HTML iconHTML

    This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floating-Point Divider Design for FPGAs

    Publication Year: 2007, Page(s):115 - 118
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (140 KB)

    Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs pre... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment

    Publication Year: 2007, Page(s):118 - 123
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (659 KB) | HTML iconHTML

    This paper presents a new VLSI-efficient algorithm for robotic exploration in a dynamic environment where the geometry of the objects or their motion trajectories are not known a priori. The input to the proposed algorithm is a list of G nodes obtained using the robot's step size and the dimensions of the environment. P nodes accessible to the robot are identified. The time complexity of the propo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Order form for reprints

    Publication Year: 2007, Page(s): 124
    Request permission for commercial reuse | PDF file iconPDF (345 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2007, Page(s): C3
    Request permission for commercial reuse | PDF file iconPDF (26 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2007, Page(s): C4
    Request permission for commercial reuse | PDF file iconPDF (29 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu