Scheduled System Maintenance
On Friday, October 20, IEEE Xplore will be unavailable from 9:00 PM-midnight ET. We apologize for the inconvenience.
Notice: There is currently an issue with the citation download feature. Learn more.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 12 • Dec. 2006

Filter Results

Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2006, Page(s): C1
    Request permission for commercial reuse | PDF file iconPDF (41 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): C2
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • Editorial: New Members of the TVLSI Editorial Board

    Publication Year: 2006, Page(s):1293 - 1294
    Request permission for commercial reuse | PDF file iconPDF (520 KB)
    Freely Available from IEEE
  • Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors

    Publication Year: 2006, Page(s):1295 - 1308
    Cited by:  Papers (20)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1306 KB) | HTML iconHTML

    Embedded system security is often compromised when "trusted" software is subverted to result in unintended behavior, such as leakage of sensitive data or execution of malicious code. Several countermeasures have been proposed in the literature to counteract these intrusions. A common underlying theme in most of them is to define security policies at the system level in an application-independent m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

    Publication Year: 2006, Page(s):1309 - 1321
    Cited by:  Papers (108)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1553 KB) | HTML iconHTML

    We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison

    Publication Year: 2006, Page(s):1322 - 1335
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB) | HTML iconHTML

    In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on the supply voltage fluctuations, which are a major contribution to the delay uncertainty, which in turn limits the speed performance of current VLSI circuits. Analytical models of the delay sensitivity with respect to supply variations are derived by following a simplifi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies

    Publication Year: 2006, Page(s):1336 - 1346
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB) | HTML iconHTML

    di/dt and IR events may cause large supply voltage variations and ohmic losses due to system parasitics. Today, decoupling capacitance is used to minimize the supply voltage variation, and parallelism in the power delivery path is used to reduce ohmic loss. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, dist... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies

    Publication Year: 2006, Page(s):1347 - 1353
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1303 KB) | HTML iconHTML

    A monolithic implementation of series connected MOSFETs for high-voltage switching applications is presented. Using a single low-voltage control signal to trigger the bottom MOSFET in the series stack, a voltage division across parasitic and inserted capacitances in the circuit is used to turn on the entire stack of devices. This voltage division both statically and dynamically safeguards the indi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and Application of Adaptive Delay Sequential Elements

    Publication Year: 2006, Page(s):1354 - 1367
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB) | HTML iconHTML

    Lower operating voltages and faster clock frequencies in advanced fabrication processes increase the circuit delay sensitivity to voltage, temperature, and process variations and modeling approximations. Uncorrelated delay variations along data and clock paths cause timing violations. In this paper, we propose a method for correcting timing violations by in-circuit tuning of clock latencies after ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sequential Element Design With Built-In Soft Error Resilience

    Publication Year: 2006, Page(s):1368 - 1378
    Cited by:  Papers (120)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1272 KB) | HTML iconHTML

    This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

    Publication Year: 2006, Page(s):1379 - 1383
    Cited by:  Papers (21)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (311 KB) | HTML iconHTML

    This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast Interconnect and Gate Timing Analysis for Performance Optimization

    Publication Year: 2006, Page(s):1383 - 1388
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (514 KB) | HTML iconHTML

    Static timing analysis is a key step in the physical design optimization of VLSI designs. The lumped capacitance model for gate delay and the Elmore model for wire delay have been shown to be inadequate for wire-dominated designs. Using the effective capacitance model for the gate delay calculation and model-order reduction techniques for wire delay calculation is prohibitively expensive. In this ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials

    Publication Year: 2006, Page(s):1388 - 1393
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (347 KB) | HTML iconHTML

    In this paper, we consider the design of bit-parallel canonical basis multipliers over the finite field GF(2m) generated by a special type of irreducible pentanomial that is used as an irreducible polynomial in the Advanced Encryption Standard (AES). Explicit formulas for the coordinates of the multiplier are given. The main advantage of our design is that some of the expressions obtain... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurate Loop Self Inductance Bound for Efficient Inductance Screening

    Publication Year: 2006, Page(s):1393 - 1397
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB) | HTML iconHTML

    An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the develop... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Publication Year: 2006, Page(s): 1398
    Request permission for commercial reuse | PDF file iconPDF (617 KB)
    Freely Available from IEEE
  • Order form for reprints

    Publication Year: 2006, Page(s): 1399
    Request permission for commercial reuse | PDF file iconPDF (354 KB)
    Freely Available from IEEE
  • Have you visited lately? www.ieee.org [advertisement]

    Publication Year: 2006, Page(s): 1400
    Request permission for commercial reuse | PDF file iconPDF (220 KB)
    Freely Available from IEEE
  • 2006 Index

    Publication Year: 2006, Page(s):1401 - 1416
    Request permission for commercial reuse | PDF file iconPDF (192 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): C3
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): C4
    Request permission for commercial reuse | PDF file iconPDF (29 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu