IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 12 • Dec. 2005

Filter Results

Displaying Results 1 - 15 of 15
  • Table of contents

    Publication Year: 2005, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (38 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (34 KB)
    Freely Available from IEEE
  • Fast comparisons of circuit implementations

    Publication Year: 2005, Page(s):1329 - 1339
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB) | HTML iconHTML

    Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associate... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wire retiming as fixpoint computation

    Publication Year: 2005, Page(s):1340 - 1348
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    In system-on-chips (SOCs), a nonnegligible part of operation time is spent on global wires with long delays. Retiming-that is moving flip-flops in a circuit without changing its functionality-can be explored to pipeline long interconnect wires in SOC designs. The problem of retiming over a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be inserted ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An overview of the competitive and adversarial approaches to designing dynamic power management strategies

    Publication Year: 2005, Page(s):1349 - 1361
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (579 KB) | HTML iconHTML

    Dynamic power management (DPM) refers to the problem of judicious application of various low-power techniques based on runtime conditions in an embedded system to minimize the total energy consumption. To be effective, often such decisions take into account the operating conditions and the system-level design goals. DPM has been a subject of intense research in the past decade driven by the need f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits

    Publication Year: 2005, Page(s):1362 - 1375
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (937 KB) | HTML iconHTML

    Gate oxide tunneling current (I/sub gate/) is comparable to subthreshold leakage current in CMOS circuits when the equivalent physical oxide thickness (T/sub ox/) is below 15 /spl Aring/. Increasing the value of T/sub ox/ reduces the leakage at the expense of increased delay, and hence a practical tradeoff between delay and leakage can be achieved by assigning one of two permissible T/sub ox/ valu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bus encoding for total power reduction using a leakage-aware buffer configuration

    Publication Year: 2005, Page(s):1376 - 1383
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (661 KB) | HTML iconHTML

    Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We utilize a buffer design approach... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect

    Publication Year: 2005, Page(s):1384 - 1393
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    Asynchronous design offers a solution to the interconnect problems faced by system-on-chip (SoC) designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building block of asynchronous circuits. A simple method for generating test patterns is described which is show... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Configuration compression for FPGA-based embedded systems

    Publication Year: 2005, Page(s):1394 - 1398
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    Field programmable gate arrays (FPGAs) are a promising technology for developing high-performance embedded systems. The density and performance of FPGAs have drastically improved over the past few years. Consequently, the size of the configuration bit-streams has also increased considerably. As a result, the cost-effectiveness of FPGA-based embedded systems is significantly affected by the memory ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multiparameter implantable microstimulator SOC

    Publication Year: 2005, Page(s):1399 - 1402
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (657 KB) | HTML iconHTML

    Various implantable microstimulators have been proposed for clinical applications in recent years. Most of the no-battery implanted devices can be powered by a transcutaneous magnetic coupling, which basically utilizes an external transmitter coil to power and communicate with the implanted device. Small chip area and low power consumption are the keys of the implanted device. Therefore, we propos... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE International SOC Conference (SOCC)

    Publication Year: 2005, Page(s): 1403
    Request permission for commercial reuse | PDF file iconPDF (521 KB)
    Freely Available from IEEE
  • IEEE order form for reprints

    Publication Year: 2005, Page(s): 1404
    Request permission for commercial reuse | PDF file iconPDF (354 KB)
    Freely Available from IEEE
  • 2005 Index

    Publication Year: 2005, Page(s):1405 - 1420
    Request permission for commercial reuse | PDF file iconPDF (304 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (30 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu