IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 4 • April 2005

Filter Results

Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2005, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (41 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2005, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (32 KB)
    Freely Available from IEEE
  • Fast factorization architecture in soft-decision Reed-Solomon decoding

    Publication Year: 2005, Page(s):413 - 426
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (621 KB) | HTML iconHTML

    Reed-Solomon (RS) codes are among the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to its hard-decision counterpart, soft-decision decoding offers considerably higher error-correcting capability. The recent development of soft-decision RS decoding algorithms makes their hardware implementations feasible. Among these algorithms, the Koette... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

    Publication Year: 2005, Page(s):427 - 438
    Cited by:  Papers (35)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (766 KB) | HTML iconHTML

    Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is e... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VLSI architectural design tradeoffs for sliding-window log-MAP decoders

    Publication Year: 2005, Page(s):439 - 447
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    Turbo codes have received tremendous attention and have commenced their practical applications due to their excellent error-correcting capability. Investigation of efficient iterative decoder realizations is of particular interest because the underlying soft-input soft-output decoding algorithms usually lead to highly complicated implementation. This paper describes the architectural design and an... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication

    Publication Year: 2005, Page(s):448 - 461
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1299 KB) | HTML iconHTML

    This paper demonstrates the design of efficient asynchronous bundled-data pipelines for the matrix-vector multiplication core of discrete cosine transforms (DCTs). The architecture is optimized for both zero and small-valued data, typical in DCT applications, yielding both high average performance and low average power. The proposed bundled-data pipelines include novel data-dependent delay lines w... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Self-reset logic for fast arithmetic applications

    Publication Year: 2005, Page(s):462 - 475
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1157 KB) | HTML iconHTML

    A new family of self-reset logic (SRL) cells is presented in this paper. The single-ended basic structure proposed realizes an incomplete logic family, since it is incapable of inverting logic. Thus, a dual-rail SRL (DRSRL) implementation is also proposed. These cells maintain small delay variations for all input combinations, once minimum timing requirements on inputs are satisfied, and produce o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A digit-serial multiplier for finite field GF(2/sup m/)

    Publication Year: 2005, Page(s):476 - 483
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (709 KB) | HTML iconHTML

    In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2/sup m/) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A reconfigurable, power-efficient adaptive Viterbi decoder

    Publication Year: 2005, Page(s):484 - 488
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (262 KB) | HTML iconHTML

    Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these implementations require an exponential increase in very large scale integration area and power consumption to achieve inc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of multigigabit multiplexer-loop-based decision feedback equalizers

    Publication Year: 2005, Page(s):489 - 493
    Cited by:  Papers (20)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB) | HTML iconHTML

    This paper presents novel approaches for pipelining of parallel nested multiplexer loops and decision feedback equalizers (DFEs) based on look-ahead techniques. Look-ahead techniques can be applied to pipeline a nested multiplexer loop in many possible ways. It is shown that not all the look-ahead approaches necessarily result in improved performance. A novel look-ahead approach is identified, whi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Memory sub-banking scheme for high throughput MAP-based SISO decoders

    Publication Year: 2005, Page(s):494 - 498
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB) | HTML iconHTML

    The sliding window (SW) approach has been proposed as an effective means of reducing the memory requirements as well as the decoding latency of the maximum a posteriori (MAP) based soft-input soft-output (SISO) decoder in a Turbo decoder. In this paper, we present sub-banked memory implementations (both single port and dual port) of the SW SISO decoder that achieves high throughput, low decoding l... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Instruction code mapping for performance increase and energy reduction in embedded computer systems

    Publication Year: 2005, Page(s):498 - 502
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB) | HTML iconHTML

    In this paper, we present a novel and fast constructive technique that relocates the instruction code in such a manner into the main memory that the cache is utilized more efficiently. The technique is applied as a preprocessing step, i.e., before the code is executed. Our technique is applicable in embedded systems where the number and characteristics of tasks running on the system is known a pri... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel wavelet transform-based transient current analysis for fault detection and localization

    Publication Year: 2005, Page(s):503 - 507
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB) | HTML iconHTML

    Transient current (IDD) testing has been often cited and investigated as an alternative and/or supplement to quiescent current (IDDQ) testing. In this correspondence, we present a novel integrated method for fault detection and localization using wavelet transform-based IDD waveform analysis. The time-frequency resolution property of wavelet transform helps us detect as well as localize faults in ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Erratum

    Publication Year: 2005, Page(s): 508
    Request permission for commercial reuse | PDF file iconPDF (59 KB)
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • International Symposium on Low Power Electronics and Design (ISLPED'05)

    Publication Year: 2005, Page(s): 509
    Request permission for commercial reuse | PDF file iconPDF (744 KB)
    Freely Available from IEEE
  • Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

    Publication Year: 2005, Page(s): 510
    Request permission for commercial reuse | PDF file iconPDF (523 KB)
    Freely Available from IEEE
  • Quality without compromise [advertisement]

    Publication Year: 2005, Page(s): 511
    Request permission for commercial reuse | PDF file iconPDF (319 KB)
    Freely Available from IEEE
  • IEEE order form for reprints

    Publication Year: 2005, Page(s): 512
    Request permission for commercial reuse | PDF file iconPDF (378 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2005, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (29 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2005, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu