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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 1 • Date Jan. 2005

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

The CSI multimedia architecture

Execution cache-based microarchitecture for power-efficient superscalar processors

A process-tolerant cache architecture for improved yield in nanoscale technologies

Optimum and heuristic synthesis of multiple word-length architectures

Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations

Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors

Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers

Layout techniques for FPGA switch blocks

On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms

A robust self-calibrating transmission scheme for on-chip networks

Synchronization overhead in SOC compressed test

VLSI implementation of new arithmetic residue to binary decoders

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

Call for participation for 2005 IEEE International Symposium on Circuits and Systems (ISCAS2005)

International Symposium on Low Power Electronics and Design (ISLPED'05)

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