By Topic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 4 • Date April 2004

Filter Results

Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2004, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (43 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2004, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (33 KB)
    Freely Available from IEEE
  • Guest Editorial

    Publication Year: 2004, Page(s):337 - 338
    Request permission for commercial reuse | PDF file iconPDF (45 KB) | HTML iconHTML
    Freely Available from IEEE
  • Toward the accurate prediction of placement wire length distributions in VLSI circuits

    Publication Year: 2004, Page(s):339 - 348
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB) | HTML iconHTML

    Since its introduction, Donath's technique for predicting placement wire length distributions has become one of the most popular techniques for a priori wire length estimation. However, in its original form, it was heavily constrained by the underlying circuit and architecture models. In this paper, we show how a careful relaxation of those constraints results in very high correlations between pre... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An electromigration and thermal model of power wires for a priori high-level reliability prediction

    Publication Year: 2004, Page(s):349 - 358
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (638 KB) | HTML iconHTML

    In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigra... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calibration of Rent's rule models for three-dimensional integrated circuits

    Publication Year: 2004, Page(s):359 - 366
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (550 KB) | HTML iconHTML

    In this paper, we determine the accuracy of Rahman's interconnect prediction model for three-dimensional (3-D) integrated circuits. Utilizing this model, we calculate the wiring requirement for a set of benchmark standard-cell circuits. We then obtain placed and routed wirelength figures for these circuits using 3-D standard-cell placement and global-routing tools we have developed. We find that t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Global interconnect design in a three-dimensional system-on-a-chip

    Publication Year: 2004, Page(s):367 - 372
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    A stochastic model for the global net-length distribution of a three-dimensional system-on-a-chip (3D-SoC) is derived. Using the results of this model, a global interconnect design window for a 3D-SoC is established by evaluating the constraints of: 1) wiring area; 2) clock wiring bandwidth; and 3) crosstalk noise. This window elucidates the optimum 3D-SoC global interconnect parameters for minimu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interconnect-based system-level energy and power prediction to guide architecture exploration

    Publication Year: 2004, Page(s):373 - 380
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB) | HTML iconHTML

    We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pipeline) with confidence that the final implementation will meet power and energy as well as cost and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On metrics for comparing interconnect estimation methods for FPGAs

    Publication Year: 2004, Page(s):381 - 385
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (246 KB) | HTML iconHTML

    Interconnect management is a critical design issue for large field-programmable gate arrays (FPGA) based designs. One of the most important issues for planning interconnection is the ability to reliably and efficiently predict the interconnect requirements of a given design on a given FPGA architecture. Many interconnect estimation methods have been reported so far and the estimation problem is al... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Scaling trends of on-chip power distribution noise

    Publication Year: 2004, Page(s):386 - 394
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (457 KB) | HTML iconHTML

    The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling beha... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects

    Publication Year: 2004, Page(s):395 - 407
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB) | HTML iconHTML

    Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combinati... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A software/reconfigurable hardware SAT solver

    Publication Year: 2004, Page(s):408 - 419
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (594 KB) | HTML iconHTML

    This paper introduces a novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, allows the total problem solving time to be reduced compared to other approaches that have been proposed. Moreover, the technique permits problems that exceed the resource... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • From application descriptions to hardware in seconds: a logic-based approach to bridging the gap

    Publication Year: 2004, Page(s):420 - 436
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (835 KB) | HTML iconHTML

    This paper presents a high-level hardware description environment developed at Queen's University, Belfast, U.K., which aims to bridge the gap between application design and hardware description. The environment, called application-to-hardware (A2H), allows for efficient compilation of high-level application descriptions to field programmable gate array (FPGA) hardware in the form of EDIF netlist ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling skin and proximity effects with reduced realizable RL circuits

    Publication Year: 2004, Page(s):437 - 447
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB) | HTML iconHTML

    On-chip conductors such as clock- and power-distribution networks require accurately modeling skin and proximity effects. Furthermore, to incorporate skin and proximity effects in the existing generic simulation tools such as SPICE, simple-frequency independent-lumped element-circuit models are needed. A rule based RL circuit model is proposed in this paper that is realizable and predicts skin and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE International Symposium on Circuits and Systems (ISCAS 2004)

    Publication Year: 2004, Page(s): 448
    Request permission for commercial reuse | PDF file iconPDF (527 KB)
    Freely Available from IEEE
  • The 13th International Workshop on Logic & Synthesis (IWLS)

    Publication Year: 2004, Page(s): 449
    Request permission for commercial reuse | PDF file iconPDF (138 KB)
    Freely Available from IEEE
  • IEEE International Symposium on Low Power Electronics and Design (ISLPED'04)

    Publication Year: 2004, Page(s): 450
    Request permission for commercial reuse | PDF file iconPDF (163 KB)
    Freely Available from IEEE
  • IEEE Member Digital Library [advertisement]

    Publication Year: 2004, Page(s): 451
    Request permission for commercial reuse | PDF file iconPDF (178 KB)
    Freely Available from IEEE
  • Proceedings of the IEEE celebrating 92 years of in-depth coverage on emerging technologies

    Publication Year: 2004, Page(s): 452
    Request permission for commercial reuse | PDF file iconPDF (319 KB)
    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2004, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (26 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2004, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu