CDM analysis on 65nm CMOS: Pitfalls when correlating results between IO test chips and product level
Suzuki, T.; Hashimoto, K.; Isomura, N.; Yokota, N.; Marichal, O.; Sorgeloos, B.; Van Camp, B.; Keppens, B.
Page(s): 325-331 Abstract
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New protection techniques and test chip design for achieving high CDM robustness