Enabling the on-line intrinsic evolution of analog controllers
Gwaltney, D.A.; Ferguson, M.I.
Page(s): 3- 11
Digital Object Identifier 10.1109/EH.2005.21 Abstract
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Hardware evolution of analog circuits for in-situ robotic fault-recovery
Berenson, D.; Estevez, N.; Lipson, H.
Page(s): 12- 19
Digital Object Identifier 10.1109/EH.2005.30 Abstract
| Full Text: PDF (296 KB)
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EARP-1 - an evolvable analog research platform
Ramsden, E.; Greenwood, G.W.; Hunter, D.
Page(s): 20- 25
Digital Object Identifier 10.1109/EH.2005.19 Abstract
| Full Text: PDF (1176 KB)
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Evolutionary design of analog circuits with a uniform-design based multi-objective adaptive genetic algorithm
Shuguang Zhao; Licheng Jiao; Jianxun Zhao; Yuping Wang
Page(s): 26- 29
Digital Object Identifier 10.1109/EH.2005.48 Abstract
| Full Text: PDF (112 KB)
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Tuning evolvable PID controllers through a clonal selection algorithm
Amaral, J.L.M.; Amaral, J.F.M.; Tanscheit, R.; Pacheco, M.; Mesquita, A.
Page(s): 30- 33
Digital Object Identifier 10.1109/EH.2005.47 Abstract
| Full Text: PDF (160 KB)
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On the robustness achievable with stochastic development processes
Viswanathan, S.; Pollack, J.B.
Page(s): 34- 39
Digital Object Identifier 10.1109/EH.2005.38 Abstract
| Full Text: PDF (216 KB)
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A VHDL core for intrinsic evolution of discrete time filters with signal feedback
Gwaltney, D.A.; Dutton, K.
Page(s): 43- 50
Digital Object Identifier 10.1109/EH.2005.6 Abstract
| Full Text: PDF (304 KB)
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Automatic discovery of RTL benchmark circuits with predefined testability properties
Pecenka, T.; Kotasek, Z.; Sekanina, L.; Strnadel, J.
Page(s): 51- 58
Digital Object Identifier 10.1109/EH.2005.10 Abstract
| Full Text: PDF (168 KB)
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On evolution of relatively large combinational logic circuits
Stomeo, E.; Kalganova, T.; Lambert, C.; Lipnitsakya, N.; Yatskevich, Y.
Page(s): 59- 66
Digital Object Identifier 10.1109/EH.2005.37 Abstract
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Adaptive genetic algorithm based approach for evolutionary design and multi-objective optimization of logic circuits
Shuguang Zhao; Jianxun Zhao; Licheng Jiao
Page(s): 67- 72
Digital Object Identifier 10.1109/EH.2005.7 Abstract
| Full Text: PDF (128 KB)
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Evolutionary discovering of the concept of the discrete state at the transistor level
Sekanina, L.; Zebulum, R.S.
Page(s): 73- 78
Digital Object Identifier 10.1109/EH.2005.25 Abstract
| Full Text: PDF (136 KB)
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Evolved digital circuits and genome complexity
Hartmann, M.; Lehre, P.K.; Haddow, P.C.
Page(s): 79- 86
Digital Object Identifier 10.1109/EH.2005.26 Abstract
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Intrinsic evolvable hardware implementation of a robust biological development model for digital systems
Heng Liu; Miller, J.F.; Tyrrell, A.M.
Page(s): 87- 92
Digital Object Identifier 10.1109/EH.2005.32 Abstract
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Evolution of asynchronous sequential circuits
Shanthi, A.P.; Singaram, L.K.; Parthasarathi, R.
Page(s): 93- 96
Digital Object Identifier 10.1109/EH.2005.23 Abstract
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Evolving combinational logic circuits using a hybrid quantum evolution and particle swarm inspired algorithm
Moore, P.; Venayagamoorthy, G.K.
Page(s): 97- 102
Digital Object Identifier 10.1109/EH.2005.28 Abstract
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A hardware implementation of the cell matrix self-configurable architecture: the Cell Matrix MOD 88™
Macias, N.J.; Durbeck, L.J.K.
Page(s): 103- 106
Digital Object Identifier 10.1109/EH.2005.2 Abstract
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Autonomous FPGA fault handling through competitive runtime reconfiguration
DeMara, R.F.; Kening Zhang
Page(s): 109- 116
Digital Object Identifier 10.1109/EH.2005.11 Abstract
| Full Text: PDF (208 KB)
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Robust neural networks using motes
Hereford, J.M.; Kuyucu, T.
Page(s): 117- 124
Digital Object Identifier 10.1109/EH.2005.42 Abstract
| Full Text: PDF (344 KB)
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Practical concerns when evolving circuits impervious to anticipated faults
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