A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures
Yoon, J.W.; Shrivastava, A.; Sanghyun Park; Minwook Ahn; Yunheung Paek
Page(s): 1565-1578
Digital Object Identifier 10.1109/TVLSI.2008.2001746 Abstract
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A DLL Design for Testing I/O Setup and Hold Times
Cheng Jia; Milor, L.
Page(s): 1579-1592
Digital Object Identifier 10.1109/TVLSI.2008.2005522 Abstract
| Full Text: PDF (1109 KB)
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Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter
Zhengtao Yu; Xun Liu
Page(s): 1593-1601
Digital Object Identifier 10.1109/TVLSI.2008.2006477 Abstract
| Full Text: PDF (1185 KB)
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Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding
Jiangli Zhu; Xinmiao Zhang; Zhongfeng Wang
Page(s): 1602-1615
Digital Object Identifier 10.1109/TVLSI.2008.2005575 Abstract
| Full Text: PDF (590 KB)
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Adaptive Frequency-Domain Channel Estimator in 4$ ,times ,$4 MIMO-OFDM Modems
Ming-Fu Sun; Ta-Yang Juan; Kan-Si Lin; Terng-Yin Hsu
Page(s): 1616-1625
Digital Object Identifier 10.1109/TVLSI.2008.2005672 Abstract
| Full Text: PDF (1639 KB)
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Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects
Ganguly, A.; Pande, P.P.; Belzer, B.
Page(s): 1626-1639
Digital Object Identifier 10.1109/TVLSI.2008.2005722 Abstract
| Full Text: PDF (855 KB)
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A Framework for Power-Gating Functional Units in Embedded Microprocessors
Roy, S.; Ranganathan, N.; Katkoori, S.
Page(s): 1640-1649
Digital Object Identifier 10.1109/TVLSI.2008.2005774 Abstract
| Full Text: PDF (654 KB)
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Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration
Corbetta, S.; Morandi, M.; Novati, M.; Santambrogio, M.D.; Sciuto, D.; Spoletini, P.
Page(s): 1650-1654
Digital Object Identifier 10.1109/TVLSI.2008.2005670 Abstract
| Full Text: PDF (199 KB)
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Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs
Appello, D.; Bernardi, P.; Grosso, M.; Sanchez, E.; Sonza Reorda, M.
Page(s): 1654-1659
Digital Object Identifier 10.1109/TVLSI.2008.2006177 Abstract
| Full Text: PDF (432 KB)
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Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics
Lih-Yih Chiou; Shien-Chun Luo
Page(s): 1659-1663
Digital Object Identifier 10.1109/TVLSI.2008.2007959 Abstract
| Full Text: PDF (506 KB)
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