Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture
Yoonjin Kim; Mahapatra, R.N.; Ilhyun Park; Kiyoung Choi
Page(s): 593-603
Digital Object Identifier 10.1109/TVLSI.2008.2006039 Abstract
| Full Text: PDF (2091 KB)
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Low-Leakage Storage Cells for Ternary Content Addressable Memories
Mohan, N.; Sachdev, M.
Page(s): 604-612
Digital Object Identifier 10.1109/TVLSI.2008.2006040 Abstract
| Full Text: PDF (850 KB)
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Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms
Pei-Yu Huang; Yu-Min Lee
Page(s): 613-626
Digital Object Identifier 10.1109/TVLSI.2008.2006043 Abstract
| Full Text: PDF (1983 KB)
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Integrated Solar Energy Harvesting and Storage
Guilar, N.J.; Kleeburg, T.J.; Chen, A.; Yankelevich, D.R.; Amirtharajah, R.
Page(s): 627-637
Digital Object Identifier 10.1109/TVLSI.2008.2006792 Abstract
| Full Text: PDF (1609 KB)
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Low Power and High Speed Multi Threshold Voltage Interface Circuits
Tawfik, S.A.; Kursun, V.
Page(s): 638-645
Digital Object Identifier 10.1109/TVLSI.2008.2006793 Abstract
| Full Text: PDF (502 KB)
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Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems
Changyun Zhu; Zhengyu Gu; Dick, R.P.; Li Shang; Knobel, R.G.
Page(s): 646-659
Digital Object Identifier 10.1109/TVLSI.2008.2009013 Abstract
| Full Text: PDF (1236 KB)
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A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization
Klein, F.; Leao, R.; Araujo, G.; Santos, L.; Azevedo, R.
Page(s): 660-673
Digital Object Identifier 10.1109/TVLSI.2009.2013627 Abstract
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Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique
Leary, G.; Srinivasan, K.; Mehta, K.; Chatha, K.S.
Page(s): 674-687
Digital Object Identifier 10.1109/TVLSI.2008.2011205 Abstract
| Full Text: PDF (851 KB)
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A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-m CMOS Technology
Min-Sheng Kao; Jen-Ming Wu; Chih-Hsing Lin; Fan-Ta Chen; Ching-Te Chiu; Hsu, S.S.H.
Page(s): 688-696
Digital Object Identifier 10.1109/TVLSI.2009.2016726 Abstract
| Full Text: PDF (2106 KB)
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Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits
Lingappan, L.; Gangaram, V.; Jha, N.K.; Chakravarty, S.
Page(s): 697-708
Digital Object Identifier 10.1109/TVLSI.2009.2013981 Abstract
| Full Text: PDF (528 KB)
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Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
Benkrid, Abd.S.; Benkrid, K.
Page(s): 709-722
Digital Object Identifier 10.1109/TVLSI.2009.2016715 Abstract
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Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM
Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou
Page(s): 723-727
Digital Object Identifier 10.1109/TVLSI.2008.2006042 Abstract
| Full Text: PDF (383 KB)
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Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching
Loghi, M.; Azzoni, P.; Poncino, M.
Page(s): 728-732
Digital Object Identifier 10.1109/TVLSI.2009.2016720 Abstract
| Full Text: PDF (744 KB)
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