Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips
Menichelli, F.; Olivieri, M.
Page(s): 161-171
Digital Object Identifier 10.1109/TVLSI.2008.2001940 Abstract
| Full Text: PDF (802 KB)
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Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell
Grasso, A.D.; Monsurro, P.; Pennisi, S.; Scotti, G.; Trifiletti, A.
Page(s): 172-180
Digital Object Identifier 10.1109/TVLSI.2008.2003482 Abstract
| Full Text: PDF (982 KB)
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Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology
Rosenfeld, J.; Friedman, E.G.
Page(s): 181-193
Digital Object Identifier 10.1109/TVLSI.2008.2011197 Abstract
| Full Text: PDF (1553 KB)
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A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy
Bhattacharya, K.; Ranganathan, N.; Soontae Kim
Page(s): 194-206
Digital Object Identifier 10.1109/TVLSI.2008.2003236 Abstract
| Full Text: PDF (1435 KB)
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An ROBDD-Based Combinatorial Method for the Evaluation of Yield of Defect-Tolerant Systems-on-Chip
Carrasco, J.A.; Sune, V.
Page(s): 207-220
Digital Object Identifier 10.1109/TVLSI.2008.2004479 Abstract
| Full Text: PDF (658 KB)
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The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators
Vassiliadis, N.; Theodoridis, G.; Nikolaidis, S.
Page(s): 221-233
Digital Object Identifier 10.1109/TVLSI.2008.2004482 Abstract
| Full Text: PDF (1352 KB)
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Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations
Banerjee, S.; Bozorgzadeh, E.; Dutt, N.
Page(s): 234-247
Digital Object Identifier 10.1109/TVLSI.2008.2003490 Abstract
| Full Text: PDF (638 KB)
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Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend
Nielsen, S.F.; Sparso, J.; Madsen, J.
Page(s): 248-261
Digital Object Identifier 10.1109/TVLSI.2008.2005285 Abstract
| Full Text: PDF (1180 KB)
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Multi-Gb/s LDPC Code Design and Implementation
Jin Sha; Zhongfeng Wang; Minglun Gao; Li Li
Page(s): 262-268
Digital Object Identifier 10.1109/TVLSI.2008.2002487 Abstract
| Full Text: PDF (726 KB)
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A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
Paul, S.; Jayakumar, N.; Khatri, S.P.
Page(s): 269-277
Digital Object Identifier 10.1109/TVLSI.2008.2003481 Abstract
| Full Text: PDF (560 KB)
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Analysis and Modeling of Energy Consumption in RLC Tree Circuits
Alioto, M.; Palumbo, G.; Poli, M.
Page(s): 278
Digital Object Identifier 10.1109/TVLSI.2008.2004546 Abstract
| Full Text: PDF (763 KB)
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Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs
Jie Gu; Harjani, R.; Kim, C.H.
Page(s): 292-301
Digital Object Identifier 10.1109/TVLSI.2008.2004543 Abstract
| Full Text: PDF (2433 KB)
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BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture
Mottaghi-Dastjerdi, M.; Afzali-Kusha, A.; Pedram, M.
Page(s): 302-306
Digital Object Identifier 10.1109/TVLSI.2008.2004544 Abstract
| Full Text: PDF (442 KB)
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A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus
Shu-Min Li, K.; Chung-Len Lee; Chauchin Su; Chen, J.E.
Page(s): 306-311
Digital Object Identifier 10.1109/TVLSI.2008.2004548 Abstract
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CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects
Montesdeoca, J.C.G.; Montiel-Nelson, J.A.; Nooshabadi, S.
Page(s): 311-316
Digital Object Identifier 10.1109/TVLSI.2008.2004549 Abstract
| Full Text: PDF (452 KB)
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