Zuber, P.; Bahlous, O.; Ilnseher, T.; Ritter, M.; Stechele, W.
Page(s): 1-11
Digital Object Identifier 10.1109/TVLSI.2008.2001238 Abstract
| Full Text: PDF (1246 KB)
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Low-Power, High-Speed Transceivers for Network-on-Chip Communication
Schinkel, D.; Mensink, E.; Klumperink, E.; van Tuijl, E.; Nauta, B.
Page(s): 12-21
Digital Object Identifier 10.1109/TVLSI.2008.2001949 Abstract
| Full Text: PDF (806 KB)
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Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids
Jianli Zhuo; Chakrabarti, C.; Kyungsoo Lee; Naehyuck Chang; Vrudhula, S.
Page(s): 22-32
Digital Object Identifier 10.1109/TVLSI.2008.2008432 Abstract
| Full Text: PDF (1051 KB)
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Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
Mahmoodi, H.; Tirumalashetty, V.; Cooke, M.; Roy, K.
Page(s): 33-44
Digital Object Identifier 10.1109/TVLSI.2008.2008453 Abstract
| Full Text: PDF (1640 KB)
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Random Test Generation With Input Cube Avoidance
Pomeranz, I.; Reddy, S.M.
Page(s): 45-54
Digital Object Identifier 10.1109/TVLSI.2008.2001943 Abstract
| Full Text: PDF (453 KB)
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Probabilistic Error Modeling for Nano-Domain Logic Circuits
Rejimon, T.; Lingasubramanian, K.; Bhanja, S.
Page(s): 55-65
Digital Object Identifier 10.1109/TVLSI.2008.2003167 Abstract
| Full Text: PDF (830 KB)
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High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors
Zhiyi Yu; Baas, B.M.
Page(s): 66-79
Digital Object Identifier 10.1109/TVLSI.2008.2001947 Abstract
| Full Text: PDF (1011 KB)
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Fast Configurable-Cache Tuning With a Unified Second-Level Cache
Gordon-Ross, A.; Vahid, F.; Dutt, N.D.
Page(s): 80-91
Digital Object Identifier 10.1109/TVLSI.2008.2002459 Abstract
| Full Text: PDF (1940 KB)
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From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding
Muller, O.; Baghdadi, A.; Jezequel, M.
Page(s): 92-102
Digital Object Identifier 10.1109/TVLSI.2008.2003164 Abstract
| Full Text: PDF (1162 KB)
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Hierarchical Segmentation for Hardware Function Evaluation
Dong-U Lee; Cheung, R.C.C.; Luk, W.; Villasenor, J.D.
Page(s): 103-116
Digital Object Identifier 10.1109/TVLSI.2008.2003165 Abstract
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Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning
Hua Wang; Miranda, M.; Dehaene, W.; Catthoor, F.
Page(s): 117-127
Digital Object Identifier 10.1109/TVLSI.2008.2003169 Abstract
| Full Text: PDF (1314 KB)
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Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity
Jie Gu; Keane, J.; Kim, C.H.
Page(s): 128-136
Digital Object Identifier 10.1109/TVLSI.2008.2001300 Abstract
| Full Text: PDF (860 KB)
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Performance-Oriented Parameter Dimension Reduction of VLSI Circuits
Zhuo Feng; Peng Li
Page(s): 137-150
Digital Object Identifier 10.1109/TVLSI.2008.2002489 Abstract
| Full Text: PDF (1299 KB)
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Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures
Lambrechts, A.; Raghavan, P.; Jayapala, M.; Bingfeng Mei; Catthoor, F.; Verkest, D.
Page(s): 151-155
Digital Object Identifier 10.1109/TVLSI.2008.2002993 Abstract
| Full Text: PDF (616 KB)
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Decoding the Golden Code: A VLSI Design
Cerato, B.; Masera, G.; Viterbo, E.
Page(s): 156-160
Digital Object Identifier 10.1109/TVLSI.2008.2003163 Abstract
| Full Text: PDF (168 KB)
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