Guest Editorial Special Section on Application Specific Processors
Ienne, P; Petrov, P
Page(s): 1257-1258
Digital Object Identifier 10.1109/TVLSI.2008.2005245 Abstract
| Full Text: PDF (324 KB)
Rights and Permissions
Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors
Bonzini, P.; Pozzi, L.
Page(s): 1259-1267
Digital Object Identifier 10.1109/TVLSI.2008.2001863 Abstract
| Full Text: PDF (959 KB)
Rights and Permissions
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Turkington, K.; Constantinides, G.A.; Masselos, K.; Cheung, P.Y.K.
Page(s): 1268-1280
Digital Object Identifier 10.1109/TVLSI.2008.2001744 Abstract
| Full Text: PDF (978 KB)
Rights and Permissions
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
Karuri, K.; Chattopadhyay, A.; Xiaolin Chen; Kammler, D.; Ling Hao; Leupers, R.; Meyr, H.; Ascheid, G.
Page(s): 1281-1294
Digital Object Identifier 10.1109/TVLSI.2008.2002685 Abstract
| Full Text: PDF (889 KB)
Rights and Permissions
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation
Bauer, L.; Shafique, M.; Henkel, J.
Page(s): 1295-1308
Digital Object Identifier 10.1109/TVLSI.2008.2002430 Abstract
| Full Text: PDF (3922 KB)
Rights and Permissions
A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment
Vogt, T.; Wehn, N.
Page(s): 1309-1320
Digital Object Identifier 10.1109/TVLSI.2008.2002428 Abstract
| Full Text: PDF (2696 KB)
Rights and Permissions
High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter
Dang, P.
Page(s): 1321-1334
Digital Object Identifier 10.1109/TVLSI.2008.2002683 Abstract
| Full Text: PDF (504 KB)
Rights and Permissions
A Processing Path Dispatcher in Network Processor MPSoCs
Ohlendorf, R.; Meitinger, M.; Wild, T.; Herkersdorf, A.
Page(s): 1335-1345
Digital Object Identifier 10.1109/TVLSI.2008.2002048 Abstract
| Full Text: PDF (1948 KB)
Rights and Permissions
Automatic Processor Customization for Zero-Overhead Online Software Verification
Hong Lu; Forin, A.
Page(s): 1346-1357
Digital Object Identifier 10.1109/TVLSI.2008.2002047 Abstract
| Full Text: PDF (551 KB)
Rights and Permissions
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
Fan-Min Li; Cheng-Hung Lin; An-Yeu Wu
Page(s): 1358-1371
Digital Object Identifier 10.1109/TVLSI.2008.2000514 Abstract
| Full Text: PDF (3007 KB)
Rights and Permissions
A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems
Saihua Lin; Huazhong Yang; Rong Luo
Page(s): 1372-1384
Digital Object Identifier 10.1109/TVLSI.2008.2000520 Abstract
| Full Text: PDF (928 KB)
Rights and Permissions
Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture
Bing-Fei Wu; Hsin-Yuan Peng; Tung-Lung Yu
Page(s): 1385-1398
Digital Object Identifier 10.1109/TVLSI.2008.2000526 Abstract
| Full Text: PDF (3211 KB)
Rights and Permissions
Error-Resilient Motion Estimation Architecture
Varatkar, G.V.; Shanbhag, N.R.
Page(s): 1399-1412
Digital Object Identifier 10.1109/TVLSI.2008.2000675 Abstract
| Full Text: PDF (4571 KB)
Rights and Permissions
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
Sekar, K.; Lahiri, K.; Raghunathan, A.; Dey, S.
Page(s): 1413-1426
Digital Object Identifier 10.1109/TVLSI.2008.2000727 Abstract
| Full Text: PDF (1340 KB)
Rights and Permissions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information
Cart
