Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits
Yu Wang; Ku He; Rong Luo; Hui Wang; Huazhong Yang
Page(s): 1101-1113
Digital Object Identifier 10.1109/TVLSI.2008.2000523 Abstract
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A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs
Youssef, A.; Anis, M.; Elmasry, M.
Page(s): 1114-1126
Digital Object Identifier 10.1109/TVLSI.2008.2000730 Abstract
| Full Text: PDF (1128 KB)
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Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs
Coskun, A.K.; Rosing, T.T.; Whisnant, K.A.; Gross, K.C.
Page(s): 1127-1140
Digital Object Identifier 10.1109/TVLSI.2008.2000726 Abstract
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Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing
Mirhassani, M.; Ahmadi, M.; Jullien, G.A.
Page(s): 1141-1150
Digital Object Identifier 10.1109/TVLSI.2008.2000731 Abstract
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A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem
Ming-Der Shieh; Jun-Hong Chen; Hao-Hsuan Wu; Wen-Ching Lin
Page(s): 1151-1161
Digital Object Identifier 10.1109/TVLSI.2008.2000524 Abstract
| Full Text: PDF (707 KB)
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On Parallelization of High-Speed Processors for Elliptic Curve Cryptography
Jarvinen, K.; Skytta, J.
Page(s): 1162-1175
Digital Object Identifier 10.1109/TVLSI.2008.2000728 Abstract
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A Trace-Based Framework for Verifiable GALS Composition of IPs
Suhaib, S.; Mathaikutty, D.A.; Shukla, S.K.
Page(s): 1176-1186
Digital Object Identifier 10.1109/TVLSI.2008.2000869 Abstract
| Full Text: PDF (488 KB)
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An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics
Yoshikawa, T.; Hirata, T.; Ebuchi, T.; Iwata, T.; Arima, Y.; Yamauchi, H.
Page(s): 1187-1198
Digital Object Identifier 10.1109/TVLSI.2008.2000870 Abstract
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Robust Concurrent Online Testing of Network-on-Chip-Based SoCs
Bhojwani, P.S.; Mahapatra, R.N.
Page(s): 1199-1209
Digital Object Identifier 10.1109/TVLSI.2008.2000732 Abstract
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Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device
Fekete, S.P.; van der Veen, J.C.; Ahmadinia, A.; Gohringer, D.; Majer, M.; Teich, J.
Page(s): 1210-1219
Digital Object Identifier 10.1109/TVLSI.2008.2000677 Abstract
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Dynamically De-Skewable Clock Distribution Methodology
Kapoor, A.; Jayakumar, N.; Khatri, S.P.
Page(s): 1220-1229
Digital Object Identifier 10.1109/TVLSI.2008.2000729 Abstract
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Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion
Akl, C.J.; Bayoumi, M.A.
Page(s): 1230-1239
Digital Object Identifier 10.1109/TVLSI.2008.2000861 Abstract
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Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique
Dongsheng Ma; Wang, J.; Minkyu Song
Page(s): 1240-1243
Digital Object Identifier 10.1109/TVLSI.2008.2000522 Abstract
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Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Elyada, A.; Ginosar, R.; Weiser, U.
Page(s): 1243-1248
Digital Object Identifier 10.1109/TVLSI.2008.2000867 Abstract
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An Accumulator-Based Compaction Scheme For Online BIST of RAMs
Voyiatzis, I.
Page(s): 1248-1251
Digital Object Identifier 10.1109/TVLSI.2008.2000868 Abstract
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Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors
Lin Zhang; Carpenter, A.; Ciftcioglu, B.; Garg, A.; Huang, M.; Hui Wu
Page(s): 1251-1256
Digital Object Identifier 10.1109/TVLSI.2008.2000976 Abstract
| Full Text: PDF (672 KB)
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