A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling
McLaughlin, K.; Sezer, S.; Blume, H.; Yang, X.; Kupzog, F.; Noll, T.
Page(s): 781-791
Digital Object Identifier 10.1109/TVLSI.2008.2000323 Abstract
| Full Text: PDF (1088 KB)
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MCF: A Metamodeling-Based Component Composition Framework—Composing SystemC IPs for Executable System Models
Mathaikutty, D.A.; Shukla, S.K.
Page(s): 792-805
Digital Object Identifier 10.1109/TVLSI.2008.2000344 Abstract
| Full Text: PDF (698 KB)
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Profit Aware Circuit Design Under Process Variations Considering Speed Binning
Datta, A.; Bhunia, S.; Jung Hwan Choi; Mukhopadhyay, S.; Roy, K.
Page(s): 806-815
Digital Object Identifier 10.1109/TVLSI.2008.2000364 Abstract
| Full Text: PDF (1134 KB)
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Electro-Thermal Analysis of Multi-Fin Devices
Swahn, B.; Hassoun, S.
Page(s): 816-829
Digital Object Identifier 10.1109/TVLSI.2008.2000455 Abstract
| Full Text: PDF (2204 KB)
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Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers
Carbognani, F.; Buergin, F.; Felber, N.; Kaeslin, H.; Fichtner, W.
Page(s): 830-836
Digital Object Identifier 10.1109/TVLSI.2008.2000457 Abstract
| Full Text: PDF (749 KB)
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Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units
Dimitrakopoulos, G.; Galanopoulos, K.; Mavrokefalidis, C.; Nikolos, D.
Page(s): 837-850
Digital Object Identifier 10.1109/TVLSI.2008.2000458 Abstract
| Full Text: PDF (994 KB)
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Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{rm ox}$ Technology
Amelifard, B.; Fallah, F.; Pedram, M.
Page(s): 851-860
Digital Object Identifier 10.1109/TVLSI.2008.2000459 Abstract
| Full Text: PDF (621 KB)
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Case Study of Reliability-Aware and Low-Power Design
Shengqi Yang; Wenping Wang; Tiehan Lu; Wolf, W.; Vijaykrishnan, N.; Yuan Xie
Page(s): 861-873
Digital Object Identifier 10.1109/TVLSI.2008.2000460 Abstract
| Full Text: PDF (935 KB)
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New Non-Volatile Memory Structures for FPGA Architectures
Choi, D.; Kyu Choi; Villasenor, J.D.
Page(s): 874-881
Digital Object Identifier 10.1109/TVLSI.2008.2000461 Abstract
| Full Text: PDF (662 KB)
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Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues
Gayasen, A.; Narayanan, V.; Kandemir, M.; Rahman, A.
Page(s): 882-893
Digital Object Identifier 10.1109/TVLSI.2008.2000456 Abstract
| Full Text: PDF (2093 KB)
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Effective Radii of On-Chip Decoupling Capacitors
Popovich, M.; Sotman, M.; Kolodny, A.; Friedman, E.G.
Page(s): 894-907
Digital Object Identifier 10.1109/TVLSI.2008.2000454 Abstract
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On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits
Popovich, M.; Friedman, E.G.; Sotman, M.; Kolodny, A.
Page(s): 908-921
Digital Object Identifier 10.1109/TVLSI.2008.2000515 Abstract
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Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs
Xiaomeng Shi; Kiat Seng Yeo; Jian-Guo Ma; Manh Anh Do; Erping Li
Page(s): 922-926
Digital Object Identifier 10.1109/TVLSI.2008.2000445 Abstract
| Full Text: PDF (1474 KB)
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Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains
Kavousianos, X.; Kalligeros, E.; Nikolos, D.
Page(s): 926-931
Digital Object Identifier 10.1109/TVLSI.2008.2000448 Abstract
| Full Text: PDF (433 KB)
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Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion
Pomeranz, I.; Reddy, S.M.
Page(s): 931-936
Digital Object Identifier 10.1109/TVLSI.2008.2000453 Abstract
| Full Text: PDF (317 KB)
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ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network
Chua-Chin Wang; Chi-Chun Huang; Jian-Ming Huang; Chih-Yi Chang; Chih-Peng Li
Page(s): 936-939
Digital Object Identifier 10.1109/TVLSI.2008.2000594 Abstract
| Full Text: PDF (890 KB)
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