Guest Editorial Special Section on Low-Power Electronics and Design

Robust Multiple-Phase Switched-Capacitor DC–DC Power Converter With Digital Interleaving Regulation Scheme

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering

L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

Selective Writeback: Reducing Register File Pressure and Energy Consumption

GOP-Level Dynamic Thermal Management in MPEG-2 Decoding

Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect

A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories

Variability Driven Gate Sizing for Binning Yield Optimization

Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code

Data Handling Limits of On-Chip Interconnects

Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits

Test Set Development for Cache Memory in Modern Microprocessors

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method

Diagnosis Framework for Locating Failed Segments of Path Delay Faults

Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

Timing Jitter and Power Spectral Density of Random Walk Noise in VCO

Higher Radix and Redundancy Factor for Floating Point SRT Division

IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors