Guest Editorial Special Section on Configurable Computing Design—II: Hardware Level Reconfiguration

A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs

Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays

Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective

Scalable Multigigabit Pattern Matching for Packet Inspection

Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores

Architectural Modifications to Enhance the Floating-Point Performance of FPGAs

System Architecture and Implementation of MIMO Sphere Decoders on FPGA

Fast Elliptic Curve Cryptography on FPGA

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property

Exact Distribution of the Max/Min of Two Gaussian Random Variables

FPGA Implementation(s) of a Scalable Encryption Algorithm

IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors