Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware
Rauwerda, G.K.; Heysters, P.M.; Smit, G.J.M.
Page(s): 3-13
Digital Object Identifier 10.1109/TVLSI.2007.912075 Abstract
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A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Myjak, M.J.; Delgado-Frias, J.G.
Page(s): 14-23
Digital Object Identifier 10.1109/TVLSI.2007.912080 Abstract
| Full Text: PDF (441 KB)
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Run-Time Management of a MPSoC Containing FPGA Fabric Tiles
Nollet, V.; Avasare, P.; Eeckhaut, H.; Verkest, D.; Corporaal, H.
Page(s): 24-33
Digital Object Identifier 10.1109/TVLSI.2007.912097 Abstract
| Full Text: PDF (1183 KB)
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Achieving Programming Model Abstractions for Reconfigurable Computing
Andrews, D.; Sass, R.; Anderson, E.; Agron, J.; Peck, W.; Stevens, J.; Baijot, F.; Komp, E.
Page(s): 34-44
Digital Object Identifier 10.1109/TVLSI.2007.912106 Abstract
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A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors
Jingzhao Ou; Prasanna, V.K.
Page(s): 45-56
Digital Object Identifier 10.1109/TVLSI.2007.912111 Abstract
| Full Text: PDF (1096 KB)
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Reconfigurable Architecture for Network Flow Analysis
Yusuf, S.; Luk, W.; Sloman, M.; Dulay, N.; Lupu, E.C.; Brown, G.
Page(s): 57-65
Digital Object Identifier 10.1109/TVLSI.2007.912115 Abstract
| Full Text: PDF (634 KB)
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A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1
Tripp, J.L.; Gokhale, M.B.; Hansson, A..
Page(s): 66-74
Digital Object Identifier 10.1109/TVLSI.2007.912126 Abstract
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The Reconfigurable Instruction Cell Array
Khawam, S.; Nousias, I.; Milward, M.; Ying Yi; Muir, M.; Arslan, T.
Page(s): 75-85
Digital Object Identifier 10.1109/TVLSI.2007.912133 Abstract
| Full Text: PDF (1302 KB)
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The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies
Agarwal, K.; Nassif, S.
Page(s): 86-97
Digital Object Identifier 10.1109/TVLSI.2007.909792 Abstract
| Full Text: PDF (1576 KB)
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Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects
Pomeranz, I.; Reddy, S.M.
Page(s): 98-107
Digital Object Identifier 10.1109/TVLSI.2007.909796 Abstract
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Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization
Chia-Yi Chang; Hung-Ming Chen
Page(s): 108-112
Digital Object Identifier 10.1109/TVLSI.2007.912202 Abstract
| Full Text: PDF (901 KB)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors
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