SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse
Shannon, L.; Chow, P.
Page(s): 377-390
Digital Object Identifier 10.1109/TVLSI.2007.893645 Abstract
| Full Text: PDF (545 KB)
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Power and Reliability Management of SoCs
Rosing, T.S.; Mihic, K.; De Micheli, G.
Page(s): 391-403
Digital Object Identifier 10.1109/TVLSI.2007.895245 Abstract
| Full Text: PDF (1008 KB)
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An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection
Xiaoding Chen; Hsiao, M.S.
Page(s): 404-412
Digital Object Identifier 10.1109/TVLSI.2007.893657 Abstract
| Full Text: PDF (522 KB)
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On Concurrent Detection of Errors in Polynomial Basis Multiplication
Bayat-Sarmadi, S.; Hasan, M.A.
Page(s): 413-426
Digital Object Identifier 10.1109/TVLSI.2007.893659 Abstract
| Full Text: PDF (608 KB)
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Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems
Jiong Luo; Jha, N.K.; Li-Shiuan Peh
Page(s): 427-437
Digital Object Identifier 10.1109/TVLSI.2007.893660 Abstract
| Full Text: PDF (1005 KB)
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Optimal Positions of Twists in Global On-Chip Differential Interconnects
Mensink, E.; Schinkel, D.; Klumperink, E.A.M.; van Tuijl, E.; Nauta, B.
Page(s): 438-446
Digital Object Identifier 10.1109/TVLSI.2007.893661 Abstract
| Full Text: PDF (1175 KB)
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Computation of Storage Requirements for Multi-Dimensional Signal Processing Applications
Balasa, F.; Hongwei Zhu; Luican, I.I.
Page(s): 447-460
Digital Object Identifier 10.1109/TVLSI.2007.895246 Abstract
| Full Text: PDF (740 KB)
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Testable Designs of Multiple Precharged Domino Circuits
Haniotakis, T.; Tsiatouhas, Y.; Nikolos, D.; Efstathiou, C.
Page(s): 461-465
Digital Object Identifier 10.1109/TVLSI.2007.893664 Abstract
| Full Text: PDF (160 KB)
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Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis
Potlapally, N.R.; Raghunathan, A.; Ravi, S.; Jha, N.K.; Lee, R.B.
Page(s): 465-470
Digital Object Identifier 10.1109/TVLSI.2007.893665 Abstract
| Full Text: PDF (520 KB)
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High-Speed Recursion Architectures for MAP-Based Turbo Decoders
Zhongfeng Wang
Page(s): 470-474
Digital Object Identifier 10.1109/TVLSI.2007.893668 Abstract
| Full Text: PDF (472 KB)
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A Flexible Architecture for Precise Gamma Correction
Dong-U Lee; Cheung, R.C.C.; Villasenor, J.D.
Page(s): 474-478
Digital Object Identifier 10.1109/TVLSI.2007.893671 Abstract
| Full Text: PDF (391 KB)
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A Processor-In-Memory Architecture for Multimedia Compression
Jasionowski, B.J.; Lay, M.K.; Margala, M.
Page(s): 478-483
Digital Object Identifier 10.1109/TVLSI.2007.893672 Abstract
| Full Text: PDF (901 KB)
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A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes
Zhongfeng Wang; Zhiqiang Cui
Page(s): 483-488
Digital Object Identifier 10.1109/TED.2007.895247 Abstract
| Full Text: PDF (587 KB)
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A Methodology for Transistor-Efficient Supergate Design
Kagaris, D.; Haniotakis, T.
Page(s): 488-492
Digital Object Identifier 10.1109/TVLSI.2007.895248 Abstract
| Full Text: PDF (246 KB)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors
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