Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper
Amirabadi, A.; Afzali-Kusha, A.; Mortazavi, Y.; Nourani, M.
Page(s): 125-134
Digital Object Identifier 10.1109/TVLSI.2007.891097 Abstract
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Design Methodology for Global Resonant H-Tree Clock Distribution Networks
Rosenfeld, J.; Friedman, E.G.
Page(s): 135-148
Digital Object Identifier 10.1109/TVLSI.2007.893576 Abstract
| Full Text: PDF (1471 KB)
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Integrated Placement and Skew Optimization for Rotary Clocking
Venkataraman, G.; Jiang Hu; Liu, F.
Page(s): 149-158
Digital Object Identifier 10.1109/TVLSI.2007.893577 Abstract
| Full Text: PDF (673 KB)
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Interconnect Lifetime Prediction for Reliability-Aware Systems
Zhijian Lu; Wei Huang; Stan, M.R.; Skadron, K.; Lach, J.
Page(s): 159-172
Digital Object Identifier 10.1109/TVLSI.2007.893578 Abstract
| Full Text: PDF (1242 KB)
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A New Single-Ended SRAM Cell With Write-Assist
Hobson, R.F.
Page(s): 173-181
Digital Object Identifier 10.1109/TVLSI.2007.893580 Abstract
| Full Text: PDF (533 KB)
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Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs
Meyer, J.; Kocan, F.
Page(s): 182-195
Digital Object Identifier 10.1109/TVLSI.2007.893581 Abstract
| Full Text: PDF (1286 KB)
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Segmented Virtual Ground Architecture for Low-Power Embedded SRAM
Sharifkhani, M.; Sachdev, M.
Page(s): 196-205
Digital Object Identifier 10.1109/TVLSI.2007.893584 Abstract
| Full Text: PDF (1089 KB)
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A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations
Khandelwal, V.; Srivastava, A.
Page(s): 206-215
Digital Object Identifier 10.1109/TVLSI.2007.893585 Abstract
| Full Text: PDF (521 KB)
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Online Fault Tolerance for FPGA Logic Blocks
Emmert, J.M.; Stroud, C.E.; Abramovici, M.
Page(s): 216-226
Digital Object Identifier 10.1109/TVLSI.2007.891102 Abstract
| Full Text: PDF (964 KB)
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A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks
Hae-Moon Seo; YeonKug Moon; Yong-Kuk Park; Dongsu Kim; Dong-Sun Kim; Youn-Sung Lee; Kwang-Ho Won; Seong-Dong Kim; Pyung Choi
Page(s): 227-231
Digital Object Identifier 10.1109/TVLSI.2007.893586 Abstract
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Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses
Liang Zhang; Wilson, J.M.; Bashirullah, R.; Luo, L.; Jian Xu; Franzon, P.D.
Page(s): 231-236
Digital Object Identifier 10.1109/TVLSI.2007.893588 Abstract
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Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs
Jyh-Ting Lai; An-Yeu Wu; Chien-Hsiung Lee
Page(s): 236-240
Digital Object Identifier 10.1109/TVLSI.2007.893593 Abstract
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Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes
Kallakuri, S.S.; Doboli, A.
Page(s): 240-245
Digital Object Identifier 10.1109/TVLSI.2007.895003 Abstract
| Full Text: PDF (853 KB)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors
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