Efficient Synchronization for Embedded On-Chip Multiprocessors
Monchiero, M.; Palermo, G.; Silvano, C.; Villa, O.
Page(s): 1049-1062
Digital Object Identifier 10.1109/TVLSI.2006.884147 Abstract
| Full Text: PDF (1423 KB)
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High Rate Data Synchronization in GALS SoCs
Dobkin, R.; Ginosar, R.; Sotiriou, C.P.
Page(s): 1063-1074
Digital Object Identifier 10.1109/TVLSI.2006.884148 Abstract
| Full Text: PDF (1275 KB)
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Runtime Leakage Minimization Through Probability-Aware Optimization
Dongwoo Lee; Blaauw, D.; Sylvester, D.
Page(s): 1075-1088
Digital Object Identifier 10.1109/TVLSI.2006.884149 Abstract
| Full Text: PDF (1201 KB)
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Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation
Kuo-Su Hsiao; Chung-Ho Chen
Page(s): 1089-1102
Digital Object Identifier 10.1109/TVLSI.2006.884150 Abstract
| Full Text: PDF (1304 KB)
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HVS-Aware Dynamic Backlight Scaling in TFT-LCDs
Iranli, A.; Wonbok Lee; Pedram, M.
Page(s): 1103-1116
Digital Object Identifier 10.1109/TVLSI.2006.884151 Abstract
| Full Text: PDF (2334 KB)
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Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations
Cortes, L.A.; Eles, P.; Zebo Peng
Page(s): 1117-1129
Digital Object Identifier 10.1109/TVLSI.2006.884152 Abstract
| Full Text: PDF (800 KB)
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A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis
Rejimon, T.; Bhanja, S.
Page(s): 1130-1139
Digital Object Identifier 10.1109/TVLSI.2006.884165 Abstract
| Full Text: PDF (710 KB)
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Statistical Timing Yield Optimization by Gate Sizing
Sinha, D.; Shenoy, N.V.; Hai Zhou
Page(s): 1140-1146
Digital Object Identifier 10.1109/TVLSI.2006.884166 Abstract
| Full Text: PDF (661 KB)
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Highly-Parallel Decoding Architectures for Convolutional Turbo Codes
Zhiyong He; Fortier, P.; Roy, S.
Page(s): 1147-1151
Digital Object Identifier 10.1109/TVLSI.2006.884172 Abstract
| Full Text: PDF (192 KB)
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DTMOS Technique for Low-Voltage Analog Circuits
Maymandi-Nejad, M.; Sachdev, M.
Page(s): 1151-1156
Digital Object Identifier 10.1109/TVLSI.2006.884174 Abstract
| Full Text: PDF (499 KB)
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Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding
Xinmiao Zhang
Page(s): 1156-1161
Digital Object Identifier 10.1109/TVLSI.2006.884177 Abstract
| Full Text: PDF (297 KB)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors
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