Retargetable pipeline hazard detection for partially bypassed processors
Shrivastava, A.; Earlie, E.; Dutt, N.D.; Nicolau, A.
Page(s): 791-801
Digital Object Identifier 10.1109/TVLSI.2006.878468 Abstract
| Full Text: PDF (1059 KB)
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Overlay techniques for scratchpad memories in low power embedded processors
Verma, M.; Marwedel, P.
Page(s): 802-815
Digital Object Identifier 10.1109/TVLSI.2006.878469 Abstract
| Full Text: PDF (1618 KB)
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Exploiting statistical information for implementation of instruction scratchpad memory in embedded system
Janapsatya, A.; Ignjatovic, A.; Parameswaran, S.
Page(s): 816-829
Digital Object Identifier 10.1109/TVLSI.2006.878470 Abstract
| Full Text: PDF (1484 KB)
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Expression equivalence checking using interval analysis
Ghodrat, M.A.; Givargis, T.; Nicolau, A.
Page(s): 830-842
Digital Object Identifier 10.1109/TVLSI.2006.878471 Abstract
| Full Text: PDF (959 KB)
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Probabilistic delay budget assignment for synthesis of soft real-time applications
Ghiasi, S.; Po-Kuan Huang; Jafari, R.
Page(s): 843-853
Digital Object Identifier 10.1109/TVLSI.2006.878472 Abstract
| Full Text: PDF (995 KB)
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SHIM: a deterministic model for heterogeneous embedded systems
Edwards, S.A.; Tardieu, O.
Page(s): 854-867
Digital Object Identifier 10.1109/TVLSI.2006.878473 Abstract
| Full Text: PDF (587 KB)
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Scenario-oriented design for single-chip heterogeneous multiprocessors
Paul, J.M.; Thomas, D.E.; Bobrek, A.
Page(s): 868-880
Digital Object Identifier 10.1109/TVLSI.2006.878474 Abstract
| Full Text: PDF (1161 KB)
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An automated design tool for analog layouts
Lihong Zhang; Kleine, U.; Yingtao Jiang
Page(s): 881-894
Digital Object Identifier 10.1109/TVLSI.2006.878475 Abstract
| Full Text: PDF (2228 KB)
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Low-power high-performance nand match line content addressable memories
Chaudhary, V.; Clark, L.T.
Page(s): 895-905
Digital Object Identifier 10.1109/TVLSI.2006.878476 Abstract
| Full Text: PDF (1375 KB)
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Placement for large-scale floating-gate field-programable analog arrays
Baskaya, F.; Reddy, S.; Sung Kyu Lim; Anderson, D.V.
Page(s): 906-910
Digital Object Identifier 10.1109/TVLSI.2006.878477 Abstract
| Full Text: PDF (289 KB)
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Virtual memory window for application-specific reconfigurable coprocessors
Vuletic, M.; Pozzi, L.; Ienne, P.
Page(s): 910-915
Digital Object Identifier 10.1109/TVLSI.2006.878481 Abstract
| Full Text: PDF (484 KB)
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New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder
Baek, J.H.; Sunwoo, M.H.
Page(s): 915-920
Digital Object Identifier 10.1109/TVLSI.2006.878484 Abstract
| Full Text: PDF (302 KB)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors
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