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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume: 14  Issue: 6   Date: June 2006
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Automatic linearity and frequency response tests with built-in pattern generator and analyzer

Fa Dai, F.; Stroud, C.; Dayu Yang
Page(s): 561-572
Digital Object Identifier 10.1109/TVLSI.2006.878201
Abstract  | Full Text: PDF (610 KB)
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Design techniques and test methodology for low-power TCAMs

Mohan, N.; Fung, W.; Wright, D.; Sachdev, M.
Page(s): 573-586
Digital Object Identifier 10.1109/TVLSI.2006.878206
Abstract  | Full Text: PDF (1889 KB)
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Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

MacDonald, E.; Touba, N.A.
Page(s): 587-595
Digital Object Identifier 10.1109/TVLSI.2006.878209
Abstract  | Full Text: PDF (471 KB)
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The LOTTERYBUS on-chip communication architecture

Lahiri, K.; Raghunathan, A.; Lakshminarayana, G.
Page(s): 596-608
Digital Object Identifier 10.1109/TVLSI.2006.878210
Abstract  | Full Text: PDF (1247 KB)
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Architectural enhancements for network congestion control applications

Byeong Kil Lee; John, L.K.; John, E.
Page(s): 609-615
Digital Object Identifier 10.1109/TVLSI.2006.878211
Abstract  | Full Text: PDF (786 KB)
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Power minimization for dynamic PLAs

Tzyy-Kuen Tien; Chih-Shen Tsai; Shih-Chieh Chang; Chingwei Yeh
Page(s): 616-624
Digital Object Identifier 10.1109/TVLSI.2006.878213
Abstract  | Full Text: PDF (1166 KB)
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Energy efficient watermarking on mobile devices using proxy-based partitioning

Kejariwal, A.; Gupta, S.; Nicolau, A.; Dutt, N.D.; Gupta, R.
Page(s): 625-636
Digital Object Identifier 10.1109/TVLSI.2006.878218
Abstract  | Full Text: PDF (1629 KB)
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Realistic scalability of noise in dynamic circuits

Chowdhury, M.H.; Ismail, Y.I.
Page(s): 637-641
Digital Object Identifier 10.1109/TVLSI.2006.878221
Abstract  | Full Text: PDF (218 KB)
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Crosstalk modeling for coupled RLC interconnects with application to shield insertion

Junmou Zhang; Friedman, E.G.
Page(s): 641-646
Digital Object Identifier 10.1109/TVLSI.2006.878223
Abstract  | Full Text: PDF (344 KB)
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A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

Kim, C.H.; Roy, K.; Hsu, S.; Krishnamurthy, R.; Borkar, S.
Page(s): 646-649
Digital Object Identifier 10.1109/TVLSI.2006.878226
Abstract  | Full Text: PDF (677 KB)
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MICRO: a new hybrid test data compression/decompression scheme

Sunghoon Chun; YongJoon Kim; Jung-Been Im; Sungho Kang
Page(s): 649-654
Digital Object Identifier 10.1109/TVLSI.2006.878227
Abstract  | Full Text: PDF (575 KB)
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Wafer-level package interconnect options

Balachandran, J.; Brebels, S.; Carchon, G.; Kuijk, M.; Walter De Raedt; Nauwelaers, B.K.J.C.; Beyne, E.
Page(s): 654-659
Digital Object Identifier 10.1109/TVLSI.2006.878229
Abstract  | Full Text: PDF (758 KB)
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Design of flexible GF(2/sup m/) elliptic curve cryptography processors

Benaissa, M.; Wei Ming Lim
Page(s): 659-662
Digital Object Identifier 10.1109/TVLSI.2006.878235
Abstract  | Full Text: PDF (444 KB)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

Page(s):  c4- c4
Digital Object Identifier 10.1109/TVLSI.2006.881304
Abstract  | Full Text: PDF (30 KB)
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