An asynchronous architecture for modeling intersegmental neural communication
Patel, G.N.; Reid, M.S.; Schimmel, D.E.; DeWeerth, S.P.
Page(s): 97- 110
Digital Object Identifier 10.1109/TVLSI.2005.863762 Abstract
| Full Text: PDF (1376 KB)
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A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm
Hernandez, O.J.
Page(s): 111- 121
Digital Object Identifier 10.1109/TVLSI.2005.863761 Abstract
| Full Text: PDF (504 KB)
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Energy optimization of pipelined digital systems using circuit sizing and supply scaling
Dao, H.Q.; Zeydel, B.R.; Oklobdzija, V.G.
Page(s): 122- 134
Digital Object Identifier 10.1109/TVLSI.2005.863760 Abstract
| Full Text: PDF (728 KB)
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Energy management for battery-powered reconfigurable computing platforms
Khan, J.; Vemuri, R.
Page(s): 135- 147
Digital Object Identifier 10.1109/TVLSI.2005.863757 Abstract
| Full Text: PDF (768 KB)
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Low-power network-on-chip for high-performance SoC design
Kangmin Lee; Se-Joong Lee; Hoi-Jun Yoo
Page(s): 148- 160
Digital Object Identifier 10.1109/TVLSI.2005.863753 Abstract
| Full Text: PDF (1840 KB)
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Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
Guoqing Chen; Friedman, E.G.
Page(s): 161- 172
Digital Object Identifier 10.1109/TVLSI.2005.863750 Abstract
| Full Text: PDF (704 KB)
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A combined gate replacement and input vector control approach for leakage current reduction
Lin Yuan; Gang Qu
Page(s): 173- 182
Digital Object Identifier 10.1109/TVLSI.2005.863747 Abstract
| Full Text: PDF (592 KB)
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A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET
Mukhopadhyay, S.; Mahmoodi, H.; Roy, K.
Page(s): 183- 192
Digital Object Identifier 10.1109/TVLSI.2005.863743 Abstract
| Full Text: PDF (744 KB)
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X-masking during logic BIST and its impact on defect coverage
Yuyi Tang; Wunderlich, H.-J.; Piet Engelke; Polian, I.; Becker, B.; Schloffel, J.; Hapke, F.; Wittke, M.
Page(s): 193- 202
Digital Object Identifier 10.1109/TVLSI.2005.863742 Abstract
| Full Text: PDF (872 KB)
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Layout-driven architecture synthesis for high-speed digital filters
Dongku Kang; Choo, H.; Muhammad, K.; Roy, K.
Page(s): 203- 207
Digital Object Identifier 10.1109/TVLSI.2005.863741 Abstract
| Full Text: PDF (320 KB)
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A low-power correlation-derivative CMOS VLSI circuit for bearing estimation
Julian, P.; Andreou, A.G.; Goldberg, D.H.
Page(s): 207- 212
Digital Object Identifier 10.1109/TVLSI.2005.863740 Abstract
| Full Text: PDF (632 KB)
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Comments on "Carry checking/parity prediction adders and ALUs"
Rodriguez-Navarro, J.J.
Page(s): 212- 213
Digital Object Identifier 10.1109/TVLSI.2005.863739 Abstract
| Full Text: PDF (120 KB)
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2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
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