Karandikar, S.K.; Sapatnekar, S.S.
Page(s): 1329- 1339
Digital Object Identifier 10.1109/TVLSI.2005.862727 Abstract
| Full Text: PDF (696 KB)
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Wire retiming as fixpoint computation
Chuan Lin; Hai Zhou
Page(s): 1340- 1348
Digital Object Identifier 10.1109/TVLSI.2005.862726 Abstract
| Full Text: PDF (408 KB)
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An overview of the competitive and adversarial approaches to designing dynamic power management strategies
Irani, S.; Singh, G.; Shukla, S.K.; Gupta, R.K.
Page(s): 1349- 1361
Digital Object Identifier 10.1109/TVLSI.2005.862725 Abstract
| Full Text: PDF (592 KB)
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Gate oxide leakage and delay tradeoffs for dual-Tox circuits
Sultania, A.K.; Sylvester, D.; Sapatnekar, S.S.
Page(s): 1362- 1375
Digital Object Identifier 10.1109/TVLSI.2005.862723 Abstract
| Full Text: PDF (952 KB)
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Bus encoding for total power reduction using a leakage-aware buffer configuration
Rao, R.R.; Deogun, H.S.; Blaauw, D.; Sylvester, D.
Page(s): 1376- 1383
Digital Object Identifier 10.1109/TVLSI.2005.862718 Abstract
| Full Text: PDF (672 KB)
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Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
Efthymiou, A.; Bainbridge, J.; Edwards, D.
Page(s): 1384- 1393
Digital Object Identifier 10.1109/TVLSI.2005.862722 Abstract
| Full Text: PDF (520 KB)
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Configuration compression for FPGA-based embedded systems
Dandalis, A.; Prasanna, V.K.
Page(s): 1394- 1398
Digital Object Identifier 10.1109/TVLSI.2005.862721 Abstract
| Full Text: PDF (160 KB)
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A multiparameter implantable microstimulator SOC
Chua-Chin Wang; Tzung-Je Lee; Yu-Tzu Hsiao; Chio, U.F.; Chi-Chun Huang; Chin, J.-J.J.; Ya-Hsin Hsueh
Page(s): 1399- 1402
Digital Object Identifier 10.1109/TVLSI.2005.862719 Abstract
| Full Text: PDF (672 KB)
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