Ranganathan, N.
Page(s): 773- 782
Digital Object Identifier 10.1109/TVLSI.2005.854285 Abstract
| Full Text: PDF (2256 KB)
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Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks
Lakshminarayanan, G.; Venkataramani, B.
Page(s): 783- 793
Digital Object Identifier 10.1109/TVLSI.2005.850086 Abstract
| Full Text: PDF (512 KB)
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Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA
Huang, J.; Tahoori, M.B.; Lombardi, F.
Page(s): 794- 807
Digital Object Identifier 10.1109/TVLSI.2005.850090 Abstract
| Full Text: PDF (768 KB)
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A VLSI architecture for watermarking in a secure still digital camera (S2DC) design
Mohanty, S.P.; Ranganathan, N.; Namballa, R.K.
Page(s): 808- 818
Digital Object Identifier 10.1109/TVLSI.2005.850095 Abstract
| Full Text: PDF (1752 KB)
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Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data
Saraswat, D.; Achar, R.; Nakhla, M.S.
Page(s): 819- 832
Digital Object Identifier 10.1109/TVLSI.2005.850098 Abstract
| Full Text: PDF (736 KB)
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A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC
Gui, P.; Kiamilev, F.E.; Wang, X.Q.; MacFadden, M.J.; Wang, X.L.; Waite, N.; Haney, M.W.; Kuznia, C.
Page(s): 833- 842
Digital Object Identifier 10.1109/TVLSI.2005.850101 Abstract
| Full Text: PDF (1968 KB)
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Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver
Sharma, A.; Birrer, P.; Arunachalam, S.K.; Xu, C.; Fiez, T.S.; Mayaram, K.
Page(s): 843- 851
Digital Object Identifier 10.1109/TVLSI.2005.850106 Abstract
| Full Text: PDF (1120 KB)
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Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment Without Increasing Test Time
Taillefer, C.S.; Roberts, G.W.
Page(s): 852- 860
Digital Object Identifier 10.1109/TVLSI.2005.850113 Abstract
| Full Text: PDF (944 KB)
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ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture
Kwon, Y.-S.; Kyung, C.-M.
Page(s): 861- 864
Digital Object Identifier 10.1109/TVLSI.2005.850117 Abstract
| Full Text: PDF (552 KB)
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A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing
Ando, H.; Tzartzanis, N.; Walker, W.W.
Page(s): 865- 868
Digital Object Identifier 10.1109/TVLSI.2005.850120 Abstract
| Full Text: PDF (304 KB)
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Voltage Setup Problem for Embedded Systems With Multiple Voltages
Hua, S.; Qu, G.
Page(s): 869- 872
Digital Object Identifier 10.1109/TVLSI.2005.850122 Abstract
| Full Text: PDF (208 KB)
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High-Speed Architectures for Parallel Long BCH Encoders
Zhang, X.; Parhi, K.K.
Page(s): 872- 877
Digital Object Identifier 10.1109/TVLSI.2005.850125 Abstract
| Full Text: PDF (320 KB)
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A Case for Asymmetric-Cell Cache Memories
Moshovos, A.; Falsafi, B.; Najm, F.N.; Azizi, N.
Page(s): 877- 881
Digital Object Identifier 10.1109/TVLSI.2005.850127 Abstract
| Full Text: PDF (424 KB)
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2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
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