Piguet, C.; Narayanan, V.
Page(s): 129- 130
Digital Object Identifier 10.1109/TVLSI.2004.824183 Abstract
| Full Text: PDF (61 KB)
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Statistical analysis of subthreshold leakage current for VLSI circuits
Rao, R.; Srivastava, A.; Blaauw, D.; Sylvester, D.
Page(s): 131- 139
Digital Object Identifier 10.1109/TVLSI.2003.821549 Abstract
| Full Text: PDF (320 KB)
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Leakage current reduction in CMOS VLSI circuits by input vector control
Abdollahi, A.; Fallah, F.; Pedram, M.
Page(s): 140- 154
Digital Object Identifier 10.1109/TVLSI.2003.821546 Abstract
| Full Text: PDF (560 KB)
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Gate oxide leakage current analysis and reduction for VLSI circuits
Dongwoo Lee; Blaauw, D.; Sylvester, D.
Page(s): 155- 166
Digital Object Identifier 10.1109/TVLSI.2003.821553 Abstract
| Full Text: PDF (552 KB)
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Circuit and microarchitectural techniques for reducing cache leakage power
Nam Sung Kim; Flautner, K.; Blaauw, D.; Mudge, T.
Page(s): 167- 184
Digital Object Identifier 10.1109/TVLSI.2003.821550 Abstract
| Full Text: PDF (1024 KB)
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Level conversion for dual-supply systems
Ishihara, F.; Sheikh, F.; Nikolic, B.
Page(s): 185- 195
Digital Object Identifier 10.1109/TVLSI.2003.821548 Abstract
| Full Text: PDF (624 KB)
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LECTOR: a technique for leakage reduction in CMOS circuits
Hanchate, N.; Ranganathan, N.
Page(s): 196- 205
Digital Object Identifier 10.1109/TVLSI.2003.821547 Abstract
| Full Text: PDF (608 KB)
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The Chimaera reconfigurable functional unit
Hauck, S.; Fry, T.W.; Hosler, M.M.; Kao, J.P.
Page(s): 206- 217
Digital Object Identifier 10.1109/TVLSI.2003.821545 Abstract
| Full Text: PDF (376 KB)
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High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
Meng-Da Yang; An-Yeu Wu; Jyh-Ting Lai
Page(s): 218- 226
Digital Object Identifier 10.1109/TVLSI.2003.820521 Abstract
| Full Text: PDF (672 KB)
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