Scholl, C.; Moller, D.; Molitor, P.; Drechsler, R.
Page(s): 81-100
Digital Object Identifier 10.1109/43.743706 Abstract
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Automatic synthesis of extended burst-mode circuits. I.
(Specification and hazard-free implementations)
Yun, K.Y.; Dill, D.L.
Page(s): 101-117
Digital Object Identifier 10.1109/43.743711 Abstract
| Full Text: PDF (804 KB)
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Automatic synthesis of extended burst-mode circuits. II. (Automatic
synthesis)
Yun, K.Y.; Dill, D.L.
Page(s): 118-132
Digital Object Identifier 10.1109/43.743715 Abstract
| Full Text: PDF (696 KB)
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Error bound for reduced system model by Pade approximation via the
Lanczos process
Zhaojun Bai; Slone, R.D.; Smith, W.T.; Qiang Ye
Page(s): 133-141
Digital Object Identifier 10.1109/43.743719 Abstract
| Full Text: PDF (324 KB)
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Topological routing path search algorithm with incremental
routability test
Hama, T.; Etoh, H.
Page(s): 142-150
Digital Object Identifier 10.1109/43.743721 Abstract
| Full Text: PDF (196 KB)
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A DRC-based algorithm for extraction of critical areas for opens in
large VLSI circuits
Pleskacz, W.A.; Ouyang, C.H.; Maly, W.
Page(s): 151-162
Digital Object Identifier 10.1109/43.743724 Abstract
| Full Text: PDF (588 KB)
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An improved optimal algorithm for bubble-sorting-based
non-Manhattan channel routing
Substrate optimization based on semi-analytical techniques
Charbon, E.; Gharpurey, R.; Meyer, R.G.; Sangiovanni-Vincentelli, A.
Page(s): 172-190
Digital Object Identifier 10.1109/43.743727 Abstract
| Full Text: PDF (844 KB)
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SymFony: a hybrid topological-symbolic ATPG exploiting RT-level
information
Corno, F.; Glaser, U.; Prinetto, P.; Reorda, M.S.; Vierhaus, H.T.; Violante, M.
Page(s): 191-202
Digital Object Identifier 10.1109/43.743731 Abstract
| Full Text: PDF (276 KB)
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Scan-based BIST fault diagnosis
Yuejian Wu; Adham, S.M.I.
Page(s): 203-211
Digital Object Identifier 10.1109/43.743733 Abstract
| Full Text: PDF (268 KB)
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Accurate high-speed performance prediction for full differential
current-mode logic: the effect of dielectric anisotropy
Garg, A.; Le Coz, Y.L.; Greub, H.J.; Iverson, R.B.; Philhower, R.F.; Campbell, P.M.; Maier, C.A.; Steidl, S.A.; Ernest, M.W.; Kraft, R.P.; Carlough, S.R.; Perry, J.W.; Krawczyk, T.W.; McDonald, J.F.
Page(s): 212-219
Digital Object Identifier 10.1109/43.743736 Abstract
| Full Text: PDF (716 KB)
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On the design of optimal counter-based schemes for test set
embedding
Kagaris, D.; Tragoudas, S.
Page(s): 219-230
Digital Object Identifier 10.1109/43.743738 Abstract
| Full Text: PDF (360 KB)
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On determining sensitization criterion in an iterative gate sizing
process
How-Rern Lin; Ting Ting Hwang
Page(s): 231-238
Digital Object Identifier 10.1109/43.743742 Abstract
| Full Text: PDF (236 KB)
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GLFSR-a new test pattern generator for built-in-self-test
Pradhan, D.K.; Chatterjee, M.
Page(s): 238-247
Digital Object Identifier 10.1109/43.743744 Abstract
| Full Text: PDF (308 KB)
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Exterior templates for capacitance computations [interconnections]
Zemanian, A.H.; Chang, V.A.
Page(s): 248-251
Digital Object Identifier 10.1109/43.743747 Abstract
| Full Text: PDF (76 KB)
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