Code generation in the polyhedral model is easier than you think
Bastoul, C.
Page(s): 7- 16
Digital Object Identifier 10.1109/PACT.2004.1342537 Abstract
| Full Text: PDF (360 KB)
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A compiler framework for recovery code generation in general speculative optimizations
Lin, J.; Hsu, W.-C.; Yew, P.-C.; Ju, R.D.-C.; Ngai, T.-F.
Page(s): 17- 28
Digital Object Identifier 10.1109/PACT.2004.1342538 Abstract
| Full Text: PDF (331 KB)
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A multi-platform co-array Fortran compiler
Dotsenko, Y.; Coarfa, C.; Mellor-Crummey, J.
Page(s): 29- 40
Digital Object Identifier 10.1109/PACT.2004.1342539 Abstract
| Full Text: PDF (412 KB)
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Retargeting JIT compilers by using C-compiler generated executable code
Ertl, M.A.; Gregg, D.
Page(s): 41- 50
Digital Object Identifier 10.1109/PACT.2004.1342540 Abstract
| Full Text: PDF (289 KB)
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Adding limited reconfigurability to superscalar processors
Epalza, M.; Ienne, P.; Mlynek, D.
Page(s): 53- 62
Digital Object Identifier 10.1109/PACT.2004.1342541 Abstract
| Full Text: PDF (347 KB)
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Architectural support for enhanced SMT job scheduling
Settle, A.; Kihm, J.; Janiszewski, A.; Connors, D.
Page(s): 63- 73
Digital Object Identifier 10.1109/PACT.2004.1342542 Abstract
| Full Text: PDF (584 KB)
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Static placement, dynamic issue (SPDI) scheduling for EDGE architectures
Ramadass Nagarajan; Kushwaha, S.K.; Burger, D.; McKinley, K.S.; Lin, C.; Keckler, S.W.
Page(s): 74- 84
Digital Object Identifier 10.1109/PACT.2004.1342543 Abstract
| Full Text: PDF (327 KB)
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A high-performance SIMD floating point unit for BlueGene/L: architecture, compilation, and algorithm design
Bachega, L.; Siddhartha Chatterjee; Dockser, K.A.; Gunnels, J.A.; Manish Gupta; Gustavson, F.G.; Lapkowski, C.A.; Liu, G.K.; Mendell, M.P.; Wait, C.D.; Ward, T.J.C.
Page(s): 85- 96
Digital Object Identifier 10.1109/PACT.2004.1342544 Abstract
| Full Text: PDF (328 KB)
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Impact of Java memory model on out-of-order multiprocessors
Mitra, T.; Abhik Roychoudhury; Shen, Q.
Page(s): 99- 110
Digital Object Identifier 10.1109/PACT.2004.1342545 Abstract
| Full Text: PDF (313 KB)
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Fair cache sharing and partitioning in a chip multiprocessor architecture
Kim, S.; Chandra, D.; Solihin, Y.
Page(s): 111- 122
Digital Object Identifier 10.1109/PACT.2004.1342546 Abstract
| Full Text: PDF (442 KB)
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Architectural support for high speed protection of memory integrity and confidentiality in multiprocessor systems
Shi, W.; Lee, H.-H.S.; Ghosh, M.; Lu, C.
Page(s): 123- 134
Digital Object Identifier 10.1109/PACT.2004.1342547 Abstract
| Full Text: PDF (398 KB)
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AC/DC: an adaptive data cache prefetcher
Nesbit, K.J.; Dhodapkar, A.S.; Smith, J.E.
Page(s): 135- 145
Digital Object Identifier 10.1109/PACT.2004.1342548 Abstract
| Full Text: PDF (1090 KB)
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The Earth Simulator and beyond - technological considerations toward the sustained PetaFlops machine
Zhu, Y.; Magklis, G.; Scott, M.L.; Ding, C.; Albonesi, D.H.
Page(s): 153- 164
Digital Object Identifier 10.1109/PACT.2004.1342550 Abstract
| Full Text: PDF (426 KB)
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Scalable high performance cross-module inlining
Chakrabarti, D.R.; Lozano, L.A.; Li, X.D.; Hundt, R.; Liu, S.-M.
Page(s): 165- 176
Digital Object Identifier 10.1109/PACT.2004.1342551 Abstract
| Full Text: PDF (385 KB)
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Decoupled software pipelining with the synchronization array
Rangan, R.; Vachharajani, N.; Vachharajani, M.; August, D.I.
Page(s): 177- 188
Digital Object Identifier 10.1109/PACT.2004.1342552 Abstract
| Full Text: PDF (453 KB)
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