Wong, J.L.; Gang Qu; Potkonjak, M.
Page(s): 553- 561
Digital Object Identifier 10.1109/TVLSI.2004.827567 Abstract
| Full Text: PDF (408 KB)
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A framework for energy and transient power reduction during behavioral synthesis
Mohanty, S.P.; Ranganathan, N.
Page(s): 562- 572
Digital Object Identifier 10.1109/TVLSI.2004.827568 Abstract
| Full Text: PDF (432 KB)
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Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
Chabini, N.; Wolf, W.
Page(s): 573- 589
Digital Object Identifier 10.1109/TVLSI.2004.827569 Abstract
| Full Text: PDF (976 KB)
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Input space adaptive design: a high-level methodology for optimizing energy and performance
Weidong Wang; Raghunathan, A.; Lakshminarayana, G.; Jha, N.K.
Page(s): 590- 602
Digital Object Identifier 10.1109/TVLSI.2004.827592 Abstract
| Full Text: PDF (888 KB)
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Efficient metrics and high-level synthesis for dynamically reconfigurable logic
Meribout, M.; Motomura, M.
Page(s): 603- 621
Digital Object Identifier 10.1109/TVLSI.2004.827564 Abstract
| Full Text: PDF (1072 KB)
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Pel reconstruction on FPGA-augmented TriMedia
Sima, M.; Cotofana, S.D.; Vassiliadis, S.; van Eijndhoven, J.T.J.; Vissers, K.A.
Page(s): 622- 635
Digital Object Identifier 10.1109/TVLSI.2004.827594 Abstract
| Full Text: PDF (816 KB)
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Implicit deductive fault simulation for complex delay fault models
Deodhar, J.V.; Tragoudas, S.
Page(s): 636- 641
Digital Object Identifier 10.1109/TVLSI.2004.827598 Abstract
| Full Text: PDF (192 KB)
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Low-latency architectures for high-throughput rate Viterbi decoders
Jun Jin Kong; Parhi, K.K.
Page(s): 642- 651
Digital Object Identifier 10.1109/TVLSI.2004.827600 Abstract
| Full Text: PDF (592 KB)
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An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs
Singh, R.; Bhat, N.
Page(s): 652- 657
Digital Object Identifier 10.1109/TVLSI.2004.827566 Abstract
| Full Text: PDF (232 KB)
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Efficient library characterization for high-level power estimation
Dhaou, I.B.; Tenhunen, H.
Page(s): 657- 661
Digital Object Identifier 10.1109/TVLSI.2004.827601 Abstract
| Full Text: PDF (296 KB)
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Modeling subthreshold SOI logic for static timing analysis
Valentian, A.; Thomas, O.; Vladimirescu, A.; Amara, A.
Page(s): 662- 669
Digital Object Identifier 10.1109/TVLSI.2004.827602 Abstract
| Full Text: PDF (424 KB)
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