The reliability issues on ASIC/memory integration by SiP (system-in-package) technology
Yong-Ha Song; Soon-Gon Kim; Kwang-Joon Rhee; Dong-Soo Cho; Taek-Soo Kim
Page(s): 7- 10 Abstract
| Full Text: PDF (363 KB)
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DES-SRAM IP-core: a SRAM embedding DES feature [secure SoC applications]
Labbe, A.; Portal, J.-M.; Perez, A.
Page(s): 11- 14
Digital Object Identifier 10.1109/SOC.2003.1241452 Abstract
| Full Text: PDF (367 KB)
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Optimal multilevel interconnect architecture aspect ratios for GSoCs
Wen-Shiu Liao; Pao-Ann Hsiung
Page(s): 21- 24
Digital Object Identifier 10.1109/SOC.2003.1241454 Abstract
| Full Text: PDF (349 KB)
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Independent clocks for peripheral modules in system-on-chip design
Watn, R.; Njolstad, T.; Berntsen, F.; Lonnum, J.F.
Page(s): 25- 28
Digital Object Identifier 10.1109/SOC.2003.1241455 Abstract
| Full Text: PDF (322 KB)
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A RT level verification method for SoC designs
Wadekar, S.A.
Page(s): 29- 32
Digital Object Identifier 10.1109/SOC.2003.1241456 Abstract
| Full Text: PDF (367 KB)
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Design of an energy-aware system-in-package for playing MP3 in wearable computing devices
Haid, J.; Weiss, R.; Schogler, W.; Manninger, M.
Page(s): 35- 38
Digital Object Identifier 10.1109/SOC.2003.1241457 Abstract
| Full Text: PDF (412 KB)
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An autonomous multiple module clock synchronization methodology for SoC
Shi-Dai Mai; Hong-Wen Lune; Ren-Chien Hsu; Chauchin Su
Page(s): 39- 42
Digital Object Identifier 10.1109/SOC.2003.1241458 Abstract
| Full Text: PDF (497 KB)
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A novel approach for IF selection of Bluetooth low-IF receiver based on system simulations
Ordu, G.; Sappok, S.; Wunderlich, R.; Heinen, S.
Page(s): 43- 46
Digital Object Identifier 10.1109/SOC.2003.1241459 Abstract
| Full Text: PDF (344 KB)
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Hardware nested looping of parameterized and embedded DSP core
Ya-Lan Tsao; Wei-Hao Chen; Wen-Sheng Cheng; Maw-Ching Lin; Shyh-Jye Jou
Page(s): 49- 52
Digital Object Identifier 10.1109/SOC.2003.1241460 Abstract
| Full Text: PDF (355 KB)
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Improved Mitchell-based logarithmic multiplier for low-power DSP applications
Mclaren, D.J.
Page(s): 53- 56
Digital Object Identifier 10.1109/SOC.2003.1241461 Abstract
| Full Text: PDF (323 KB)
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Digital signal processing at 1 GHz in a field-programmable object array
Helgemo, D.R.
Page(s): 57- 60
Digital Object Identifier 10.1109/SOC.2003.1241462 Abstract
| Full Text: PDF (357 KB)
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Automatic mismatches calibration in Hartley image-reject receiver
Elmala, M.A.I.; Embabi, S.H.K.
Page(s): 63- 66
Digital Object Identifier 10.1109/SOC.2003.1241463 Abstract
| Full Text: PDF (287 KB)
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An integrated dual-band low noise amplifier for GSM and wireless LAN applications
HiBRID-SoC: a system-on-chip architecture with two multimedia DSPs and a RISC core
Friebe, L.; Stolberg, H.-J.; Berekovic, M.; Moch, S.; Kulaczewski, M.B.; Dehnhardt, A.; Pirsch, R.
Page(s): 85- 88 Abstract
| Full Text: PDF (461 KB)
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Design and implementation of a scalable multimedia processor
Dassatti, A.; Martina, M.; Masera, G.; Molino, A.; Piccinini, G.; Vacca, F.; Zamboni, M.
Page(s): 89- 92 Abstract
| Full Text: PDF (410 KB)
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Module generator of data recovery for serial link receiver
Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology
Gursoy, Z.O.; Leblebici, Y.
Page(s): 99- 102
Digital Object Identifier 10.1109/SOC.2003.1241471 Abstract
| Full Text: PDF (395 KB)
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An area and power efficient RAKE receiver architecture for DSSS systems
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