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Solid-State Circuits, IEEE Journal of
Volume: 38  Issue: 11   Date: Nov. 2003
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Guest editorial [Special issue of the digital, memory, and signal processing sessions of the 2003 ISSCC]

Segars, S.; Sheikholeslami, A.; Fischer, S.
Page(s):  1791- 1794
Digital Object Identifier 10.1109/JSSC.2003.818123
Abstract  | Full Text: PDF (235 KB)
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Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

Maneatis, J.G.; Kim, J.; McClatchie, I.; Maxey, J.; Shankaradas, M.
Page(s):  1795- 1803
Digital Object Identifier 10.1109/JSSC.2003.818298
Abstract  | Full Text: PDF (573 KB)
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A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

Mansuri, M.; Yang, C.-K.K.
Page(s):  1804- 1812
Digital Object Identifier 10.1109/JSSC.2003.818300
Abstract  | Full Text: PDF (803 KB)
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A 10-GHz global clock distribution using coupled standing-wave oscillators

O'Mahony, F.; Yue, C.P.; Horowitz, M.A.; Wong, S.S.
Page(s):  1813- 1820
Digital Object Identifier 10.1109/JSSC.2003.818299
Abstract  | Full Text: PDF (1169 KB)
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A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

Bong-Joon Lee; Moon-Sang Hwang; Sang-Hyun Lee; Deog-Kyoon Jeong
Page(s):  1821- 1829
Digital Object Identifier 10.1109/JSSC.2003.818290
Abstract  | Full Text: PDF (1892 KB)
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40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

Kehrer, D.; Wohlmuth, H.-D.; Knapp, H.; Wurzer, M.; Scholtz, A.L.
Page(s):  1830- 1837
Digital Object Identifier 10.1109/JSSC.2003.818297
Abstract  | Full Text: PDF (2363 KB)
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Dynamic sleep transistor and body bias for active leakage power control of microprocessors

Tschanz, J.W.; Narendra, S.G.; Ye, Y.; Bloechel, B.A.; Borkar, S.; De, V.
Page(s):  1838- 1845
Digital Object Identifier 10.1109/JSSC.2003.818291
Abstract  | Full Text: PDF (1164 KB)
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A 400-MT/s 6.4-GB/s multiprocessor bus interface

Muljono, H.; Beom-Taek Lee; Yanmei Tian; Yanbin Wang; Atha, M.; Huang, T.; Adachi, M.; Rusu, S.
Page(s):  1846- 1856
Digital Object Identifier 10.1109/JSSC.2003.818295
Abstract  | Full Text: PDF (2115 KB)
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A 2× load/store pipe for a low-power 1-GHz embedded processor

Zongjian Chen; Murray, D.; Nishimoto, S.; Pearce, M.; Oyker, M.; Rodriguez, D.; Rogenmoser, R.; Dongwook Suh; Supnet, E.; von Kaenel, V.R.; Yiu, G.
Page(s):  1857- 1865
Digital Object Identifier 10.1109/JSSC.2003.818296
Abstract  | Full Text: PDF (863 KB)
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A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

Hoskote, Y.; Bloechel, B.A.; Dermer, G.E.; Erraguntla, V.; Finan, D.; Howard, J.; Klowden, D.; Narendra, S.G.; Ruhl, G.; Tschanz, J.W.; Sriram Vangal; Veeramachaneni, V.; Wilson, H.; Jianping Xu; Borkar, N.
Page(s):  1866- 1875
Digital Object Identifier 10.1109/JSSC.2003.818294
Abstract  | Full Text: PDF (1699 KB)
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A VLIW processor with reconfigurable instruction set for embedded applications

Lodi, A.; Toma, M.; Campi, F.; Cappelli, A.; Canegallo, R.; Guerrieri, R.
Page(s):  1876- 1886
Digital Object Identifier 10.1109/JSSC.2003.818292
Abstract  | Full Text: PDF (1712 KB)
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A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache

Rusu, S.; Stinson, J.; Tam, S.; Leung, J.; Muljono, H.; Cherkauer, B.
Page(s):  1887- 1895
Digital Object Identifier 10.1109/JSSC.2003.818293
Abstract  | Full Text: PDF (1999 KB)
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A 1.3-GHz fifth-generation SPARC64 microprocessor

Ando, H.; Yoshida, Y.; Inoue, A.; Sugiyama, I.; Asakawa, T.; Morita, K.; Muta, T.; Motokurumada, T.; Okada, S.; Yamashita, H.; Satsukawa, Y.; Konmoto, A.; Yamashita, R.; Sugiyama, H.
Page(s):  1896- 1905
Digital Object Identifier 10.1109/JSSC.2003.818146
Abstract  | Full Text: PDF (1120 KB)
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A 0.24-μm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme

Gitae Jeong; Wooyoung Cho; Ahn, S.; Hongsik Jeong; Gwanhyeob Koh; Youngnam Hwang; Kim, K.
Page(s):  1906- 1910
Digital Object Identifier 10.1109/JSSC.2003.818145
Abstract  | Full Text: PDF (541 KB)
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A 32-Mb chain FeRAM with segment/stitch array architecture

Shiratake, S.; Miyakawa, T.; Takeuchi, Y.; Ogiwara, R.; Kamoshida, M.; Hoya, K.; Oikawa, K.; Ozaki, T.; Kunishima, I.; Yamakawa, K.; Sugimoto, S.; Takashima, D.; Joachim, H.-O.; Rehm, N.; Wohlfahrt, J.; Nagel, N.; Beitel, G.; Jacob, M.; Roehr, T.
Page(s):  1911- 1919
Digital Object Identifier 10.1109/JSSC.2003.818161
Abstract  | Full Text: PDF (962 KB)
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512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

Johnson, M.; Al-Shamma, A.; Bosch, D.; Crowley, M.; Farmwald, M.; Fasoli, L.; Ilkbahar, A.; Kleveland, B.; Lee, T.; Tz-yi Liu; Quang Nguyen; Scheuerlein, R.; So, K.; Thorp, T.
Page(s):  1920- 1928
Digital Object Identifier 10.1109/JSSC.2003.818147
Abstract  | Full Text: PDF (904 KB)
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A 1.8-V 128-Mb 125-MHz multilevel cell flash memory with flexible read while write

Elmhurst, D.; Goldman, M.
Page(s):  1929- 1933
Digital Object Identifier 10.1109/JSSC.2003.818144
Abstract  | Full Text: PDF (526 KB)
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A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

Lee, J.; Sung-Soo Lee; Oh-Suk Kwon; Kyeong-Han Lee; Dae-Seok Byeon; In-Young Kim; Kyoung-Hwa Lee; Young-Ho Lim; Byung-Soon Choi; Jong-Sik Lee; Wang-Chul Shin; Jeong-Hyuk Choi; Kang-Deog Suh
Page(s):  1934- 1942
Digital Object Identifier 10.1109/JSSC.2003.818143
Abstract  | Full Text: PDF (1080 KB)
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A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

Uk-Rae Cho; Tae-Hyoung Kim; Yong-Jin Yoon; Jong-Cheol Lee; Dae-Gi Bae; Nam-Seog Kim; Kang-Young Kim; Young-Jae Son; Jeong-Suk Yang; Kwon-Il Sohn; Sung-Tae Kim; In-Yeol Lee; Kwang-Jin Lee; Tae-Gyoung Kang; Su-Chul Kim; Kee-Sik Ahn; Hyun-Geun Byun
Page(s):  1943- 1951
Digital Object Identifier 10.1109/JSSC.2003.818137
Abstract  | Full Text: PDF (850 KB)
Rights and Permissions
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

Osada, K.; Saitoh, Y.; Ibe, E.; Ishibashi, K.
Page(s):  1952- 1957
Digital Object Identifier 10.1109/JSSC.2003.818138
Abstract  | Full Text: PDF (692 KB)
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A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories

Arsovski, I.; Sheikholeslami, A.
Page(s):  1958- 1966
Digital Object Identifier 10.1109/JSSC.2003.818139
Abstract  | Full Text: PDF (652 KB)
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An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

Taito, Y.; Tanizaki, T.; Kinoshita, M.; Igaue, F.; Fujino, T.; Arimoto, K.
Page(s):  1967- 1973
Digital Object Identifier 10.1109/JSSC.2003.818142
Abstract  | Full Text: PDF (835 KB)
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A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

Pilo, H.; Anand, D.; Barth, J.; Burns, S.; Corson, P.; Covino, J.; Lamphier, S.
Page(s):  1974- 1980
Digital Object Identifier 10.1109/JSSC.2003.818141
Abstract  | Full Text: PDF (1162 KB)
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A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications

Okamoto, K.; Morie, T.; Yamamoto, A.; Nagano, K.; Sushihara, K.; Nakahira, H.; Horibe, R.; Aida, K.; Takahashi, T.; Ochiai, M.; Soneda, A.; Kakiage, T.; Iwasaki, T.; Taniuchi, H.; Shibata, T.; Ochi, T.; Takiguchi, M.; Yamamoto, T.; Seike, T.; Matsuzawa, A.
Page(s):  1981- 1991
Digital Object Identifier 10.1109/JSSC.2003.818131
Abstract  | Full Text: PDF (1564 KB)
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A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements

Kyo, S.; Koga, T.; Okazaki, S.; Kuroda, I.
Page(s):  1992- 2000
Digital Object Identifier 10.1109/JSSC.2003.818128
Abstract  | Full Text: PDF (832 KB)
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