Vivek De; Benini, L.
Page(s): 753- 754
Digital Object Identifier 10.1109/TVLSI.2003.818875 Abstract
| Full Text: PDF (193 KB)
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VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
Hyunsik Im; Inukai, T.; Gomyo, H.; Hiramoto, T.; Sakurai, T.
Page(s): 755- 761
Digital Object Identifier 10.1109/TVLSI.2003.814320 Abstract
| Full Text: PDF (508 KB)
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Voltage-pulse driven harmonic resonant rail drivers for low-power applications
Joong-Seok Moon; Athas, W.C.; Soli, S.D.; Draper, J.T.; Beerel, P.A.
Page(s): 762- 777
Digital Object Identifier 10.1109/TVLSI.2003.814323 Abstract
| Full Text: PDF (1125 KB)
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Optimization of scannable latches for low energy
Zyuban, V.
Page(s): 778- 788
Digital Object Identifier 10.1109/TVLSI.2003.814322 Abstract
| Full Text: PDF (903 KB)
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Energy-efficient issue queue design
Ponomarev, D.V.; Kucuk, G.; Ergin, O.; Ghose, K.; Kogge, P.M.
Page(s): 789- 800
Digital Object Identifier 10.1109/TVLSI.2003.814321 Abstract
| Full Text: PDF (759 KB)
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Micro-operation cache: a power aware frontend for variable instruction length ISA
Solomon, B.; Mendelson, A.; Ronen, R.; Orenstien, D.; Almog, Y.
Page(s): 801- 811
Digital Object Identifier 10.1109/TVLSI.2003.814327 Abstract
| Full Text: PDF (1496 KB)
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Application-directed voltage scaling
Pouwelse, J.; Langendoen, K.; Sips, H.J.
Page(s): 812- 826
Digital Object Identifier 10.1109/TVLSI.2003.814324 Abstract
| Full Text: PDF (628 KB)
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Adaptive low-power address encoding techniques using self-organizing lists
Mamidipaka, M.N.; Hirschberg, D.S.; Dutt, N.D.
Page(s): 827- 834
Digital Object Identifier 10.1109/TVLSI.2003.814325 Abstract
| Full Text: PDF (462 KB)
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A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers
Mostafa, M.A.I.; Embabi, S.H.K.; Elmala, M.
Page(s): 835- 838
Digital Object Identifier 10.1109/TVLSI.2003.814326 Abstract
| Full Text: PDF (519 KB)
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Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters
Singh, M.; Koren, I.
Page(s): 839- 852
Digital Object Identifier 10.1109/TVLSI.2003.812376 Abstract
| Full Text: PDF (896 KB)
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Test data compression and test time reduction using an embedded microprocessor
Sungbae Hwang; Abraham, J.A.
Page(s): 853- 862
Digital Object Identifier 10.1109/TVLSI.2003.817140 Abstract
| Full Text: PDF (561 KB)
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Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ
Keshavarzi, A.; Roy, K.; Hawkins, C.F.; De, V.
Page(s): 863- 870
Digital Object Identifier 10.1109/TVLSI.2003.812298 Abstract
| Full Text: PDF (480 KB)
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A digitally programmable delay element: design and analysis
Maymandi-Nejad, M.; Sachdev, M.
Page(s): 871- 878
Digital Object Identifier 10.1109/TVLSI.2003.810787 Abstract
| Full Text: PDF (432 KB)
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Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim; Saxena, P.; Liu, C.L.; Kang, S.-M.S.
Page(s): 879- 887
Digital Object Identifier 10.1109/TVLSI.2003.817111 Abstract
| Full Text: PDF (637 KB)
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Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation
Chen, T.; Naffziger, S.
Page(s): 888- 899
Digital Object Identifier 10.1109/TVLSI.2003.817120 Abstract
| Full Text: PDF (829 KB)
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Improved model-order reduction by using spacial information in moments
Ismail, Y.I.
Page(s): 900- 908
Digital Object Identifier 10.1109/TVLSI.2003.817138 Abstract
| Full Text: PDF (450 KB)
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Modeling technology impact on cluster microprocessor performance
Codrescu, L.; Nugent, S.; Meindl, J.; Wills, D.S.
Page(s): 909- 920
Digital Object Identifier 10.1109/TVLSI.2003.817512 Abstract
| Full Text: PDF (743 KB)
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Petri net modeling of gate and interconnect delays for power estimation
Murugavel, A.K.; Ranganathan, N.
Page(s): 921- 927
Digital Object Identifier 10.1109/TVLSI.2003.817110 Abstract
| Full Text: PDF (411 KB)
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Memory allocation and mapping in high-level synthesis - an integrated approach
Jaewon Seo; Taewhan Kim; Panda, P.R.
Page(s): 928- 938
Digital Object Identifier 10.1109/TVLSI.2003.817116 Abstract
| Full Text: PDF (733 KB)
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A high-speed energy-efficient 64-bit reconfigurable binary adder
Perri, S.; Corsonello, P.; Cocorullo, G.
Page(s): 939- 943
Digital Object Identifier 10.1109/TVLSI.2003.817109 Abstract
| Full Text: PDF (450 KB)
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A dictionary-based en/decoding scheme for low-power data buses
Tiehan Lv; Henkel, J.; Lekatsas, H.; Wolf, W.
Page(s): 943- 951
Digital Object Identifier 10.1109/TVLSI.2003.817123 Abstract
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Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
Sakai, A.; Yamada, T.; Matsushita, Y.; Yasuura, H.
Page(s): 951- 954
Digital Object Identifier 10.1109/TVLSI.2003.817126 Abstract
| Full Text: PDF (338 KB)
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Design of reconfigurable access wrappers for embedded core based SoC test
Koranne, S.
Page(s): 955- 960
Digital Object Identifier 10.1109/TVLSI.2003.817128 Abstract
| Full Text: PDF (458 KB)
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