Hemink, G.J.; Meijer, B.W.; Kerkhoff, H.G.
Page(s): 573-583
Digital Object Identifier 10.1109/43.55186 Abstract
| Full Text: PDF (1040 KB)
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Multiple distributions for biased random test patterns
A realistic fault model and test algorithms for static random
access memories
Dekker, R.; Beenker, F.; Thijssen, L.
Page(s): 567-572
Digital Object Identifier 10.1109/43.55188 Abstract
| Full Text: PDF (552 KB)
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Hierarchical test generation using precomputed tests for modules
Murray, B.T.; Hayes, J.P.
Page(s): 594-603
Digital Object Identifier 10.1109/43.55189 Abstract
| Full Text: PDF (872 KB)
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Easily testable PLA-based finite state machines
Devadas, S.; Ma, H.-K.T.
Page(s): 604-611
Digital Object Identifier 10.1109/43.55190 Abstract
| Full Text: PDF (764 KB)
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Application of scan hardware and software for debug and diagnostics
in a workstation environment
Experiences with concurrent fault simulation of diagnostic programs
Demba, S.; Ulrich, E.; Lentz, K.P.; Giramma, D.
Page(s): 621-628
Digital Object Identifier 10.1109/43.55192 Abstract
| Full Text: PDF (808 KB)
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Continuous signature monitoring: low-cost concurrent detection of
processor control errors
Wilken, K.; Shen, J.P.
Page(s): 629-641
Digital Object Identifier 10.1109/43.55193 Abstract
| Full Text: PDF (1296 KB)
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Estimation of maximum currents in MOS IC logic circuits
Chowdhury, S.; Barkatullah, J.S.
Page(s): 642-654
Digital Object Identifier 10.1109/43.55194 Abstract
| Full Text: PDF (1188 KB)
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DVLASIC: catastrophic fault yield simulation in a distributed
processing environment
Walker, D.M.H.; Nydick, D.S.
Page(s): 655-664
Digital Object Identifier 10.1109/43.55195 Abstract
| Full Text: PDF (1060 KB)
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`Defensive programming' in the rapid development of a parallel
scientific program
Cheng, D.Y.; Deutsch, J.T.; Dutton, R.W.
Page(s): 665-669
Digital Object Identifier 10.1109/43.55196 Abstract
| Full Text: PDF (572 KB)
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SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in
VLSI chip layouts
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