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Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the

Date 27 June-1 July 2005

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Displaying Results 1 - 25 of 71
  • Yield challenges in nanotechnology

    Publication Year: 2005
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (110 KB) |  | HTML iconHTML  

    Summary form only given. As semiconductors enter into the era of nanotechnology, fast yield ramp becomes a critical success factor for 300-mm manufacturing, enabling quick product time to market. Hence, the implementation of enhanced yield improvement techniques is essential to meet the yield challenge. This presentation covers the state-of-the-art automation, advanced integrated yield systems, in-line process control, metrology and inspection/electrical testing and enhanced physical and failure analysis techniques for Chartered Fab 7, 300-mm nanotechnology Fab. It also demonstrates the combination of intelligent automation and advanced integrated yield system capability for providing real time, fast and accurate feedback to drive yield improvement and yield prediction. View full abstract»

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  • Testing of ultra low voltage CMOS microprocessors using the superconducting single-photon detector (SSPD)

    Publication Year: 2005
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB) |  | HTML iconHTML  

    In F. Stellari and P. Song (2004) the authors have shown a comparison among different detectors used for diagnosing integrated circuits (ICs) by means of the PICA method. In their experiments they used two versions of the SSPD detector (p-SSPD is a prototype version, while c-SSPD is the first commercially available generation of the detector as presented in W. K. Lo et al. (2002), as well as the imaging detector (S-25 photo-multiplier tube (PMT) as discussed in W. G. McMullan (1987)) used in the conventional PICA technique. A microprocessor chip fabricated in a 0.13 μm 1.2 V technology is used to show that c-SSPD provides a significant reduction in acquisition time for the collection of optical waveforms from chips running at very low. In this paper, the authors summarize the main results. View full abstract»

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  • Three dimensional imaging of microelectronic devices using a crossbeam FIB

    Publication Year: 2005
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    These experiments were performed using a Carl Zeiss 1540 crossbeam instrument that permits SEM imaging during ion milling. The FIB beam consists of 30 KV Ga ions with currents ranging from several nanoamperes down to several picoamperes. The Schottky source electron gun was run in the high current mode at 1 and 5 KV to provide an electron beam current of about 2nA. Much of the surrounding material is removed to allow for better viewing and expose the faced used to start the milling. The FIB was then set to mill through the entire region with the SEM set to capture a secondary electron image of the freshly exposed surface every 10 seconds. After these images are created they can be orientated and manipulated to provide a view of any part of the volume including slicing the volume from any arbitrary direction. After the image is collected the sample is reoriented back to the milling position. This process is repeated until the region of interest is fully eroded. View full abstract»

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  • Room temperature defect localization of hot and cold failures using scanning probe microscopy techniques

    Publication Year: 2005 , Page(s): 5 - 8
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    We have developed a defect localization technique at room temperature for devices with nano-leakage and fails only at either cold (0°C) or hot (110°C) temperature testing using conducting atomic force microscopy (C-AFM) and tunneling atomic force microscope (TUNA). With this technique, we isolated the failure to a single transistor leg (i.e. source, drain, and gate) from two test structures. C-AFM was used to isolate a 90nm CMOS test unit whose failure is stuck at zero "0" logic only at cold and at certain frequency and voltage values. TUNA was used in the second test structure, a flash device that losses charge only at hot temperature. Different sample biases were used to capture and isolate the defect site. I-V curves were obtained on the isolated abnormal contacts to verify the failure models. Defect modeling using Spice simulation was also employed to verify and understand the failure mechanism. View full abstract»

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  • Laser beam induced dielectric cracks in VLSI devices

    Publication Year: 2005 , Page(s): 9 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (629 KB) |  | HTML iconHTML  

    In this paper we first discuss details of the scanning optical microscope (SOM) used for TIVA analysis. Sample preparation and the effect of SRO deposition conditions on overall wafer stress are presented next. The use of surface acoustic wave (SAW) technique as discussed in M. Gostein et al. (2003), to calculate Young's modulus of the SRO films is discussed. Dielectric cracking results for the different sample types are shown and finally, FE modeling of samples with low and high propensity to cracking is presented. View full abstract»

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  • Novel acoustic techniques for microelectronic failure analysis and characterization

    Publication Year: 2005 , Page(s): 14 - 19
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (775 KB) |  | HTML iconHTML  

    Acoustic/phonon characterization techniques using active sample probing for localized phonon generation such as scanning electron acoustic microscopy (SEAM), scanning photo or laser acoustic microscopy (SPAM/SLAM) and scanning ion acoustic microscopy (SIAM) are recent developments as extensions of acoustic analysis. In addition to the active electron beam probing mode, passive acoustic detection could also be used in cases where intrinsic phonon generation or phonon-mediated relaxation mechanisms occur during device operation as stated in R. Lifshitz (2002). This technique is currently under active research at the National University of Singapore as a means of dynamically characterizing parameters of microelectromechanical (MEMS) devices such as RF microswitches, resonators, accelerometers and gyroscopes. View full abstract»

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  • Identification of some key parameters for photoelectric laser stimulation of IC: an experimental approach

    Publication Year: 2005 , Page(s): 21 - 26
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (443 KB) |  | HTML iconHTML  

    The aim of this paper is to give a phenomenological approach of PLS in order to establish and justify what is the right choice of key parameters to perform a specific analysis. In this paper, we mostly focus on medium and low laser power density range. Our approach is built from experimental studies done on different apparatus giving us a wide range of parameter choices: from power densities in GW/cm2 to mW/cm2 range, from continuous to ultra short pulse, from fixed position to variable slow scan. This unique opportunity, experimental results and simulation performed has contributed to extend PLS knowledge. View full abstract»

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  • Rapid diagnostics of an ASIC IP block using dynamic laser scanning

    Publication Year: 2005 , Page(s): 27 - 31
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (905 KB) |  | HTML iconHTML  

    Recently a powerful class of failure analysis techniques based on dynamic laser stimulation (DLS) of operating ICs has been developed. DLS techniques include soft-defect localization (SDL), in which a 1.3μm laser locally heats the device, and laser-assisted device alteration (LADA), in which a 1.06 μm laser injects photocurrent. In this paper we report the use of DLS to locate a marginal circuit in an IP memory block on an advanced graphics ASIC with 0.11 μm technology. View full abstract»

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  • How effective are failure analysis methods for the 65nm CMOS technology node?

    Publication Year: 2005 , Page(s): 32 - 37
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2570 KB) |  | HTML iconHTML  

    Various 65 nm CMOS technology FA case studies have been presented and it is concluded that to maintain a high FA success rate for <65nm technologies it is necessary to: (1) improve the characteristics of existing tools considerably: immersion lenses and lock-in amplifiers to improve spatial resolution and detection sensitivity of laser stimulation methods were tested. For SEM imaging, newest generation, high resolution columns exhibiting significantly better performances at low electron beam energies (< 1kV) are now in use; and (2) develop new fault isolation methods (Seebeck imaging, Electro-plating localization, RCI) to also cover the most difficult failure analyses of e.g. high resistive structures. View full abstract»

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  • Successful fault isolation of bit line leakage and leakage suppression by ILD optimization in embedded flash memory

    Publication Year: 2005 , Page(s): 38 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2207 KB) |  | HTML iconHTML  

    This paper discussed specifically by focusing on failure analysis study for the successful fault isolation of bit line to bit line (BL) leakage and the formation mechanism of electrical conducting path inside inter level dielectric (ILD) oxide between bit lines in flash cell arrays that has extra topography resulting from two stacked poly-Si layers, which causes the abnormal leakage current during the initial cycling test (a few times of erasing and programming) for flash memory device using high voltage application. In addition, we demonstrate the suppression of this leakage current by optimizing ILD deposition process, resulting in the significant yield improvement as well as better process margin across a wafer. View full abstract»

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  • Application of logic mapping in the low voltage functional failure analysis

    Publication Year: 2005 , Page(s): 43 - 46
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (698 KB) |  | HTML iconHTML  

    Logic mapping is shown to be a good debug technique to increase the PFA success rate in logic failures, especially low voltage functional failures. The faster cycle time in PFA is especially critical in today fast product yield ramp up. The results from this paper demonstrated that logic mapping is capable of isolating hard defects, which cause functional failures at all voltages in advance CMOS devices. Furthermore, we demonstrated that logic mapping is also capable of isolating VLV related failures as well. View full abstract»

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  • The physical failure analysis (PFA) of IDDQ and IDDQ_delta fail in 90nm logic products

    Publication Year: 2005 , Page(s): 47 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (879 KB) |  | HTML iconHTML  

    As part of a manufacturing test, IDDQ method has played an indispensable role within the entire fault detection process and IIDD_delta test has been identified as one of the possible ways to extend the usability of IDDQ. For the physical failure analysis (PFA) of IDDQ/IDDQ_delta failure parts, emission microscope (EMMI) is widely used for defect site localization. And then the positive voltage contrast (PVC) and the I-V curves measurement for individual contacts by C-AFM were performed to identify the precise defect location and real leakage path. The different types of defect were observed: crystal defect induced P+/NW contact leakage and poly-silicon (poly-Si) filled into shallow trench isolation (STI) voids induced leakage are the major defects in this work. View full abstract»

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  • Physical analysis of TiSi2 bridging (gate-to-S/D) failure in IC

    Publication Year: 2005 , Page(s): 52 - 55
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB) |  | HTML iconHTML  

    In this paper, the procedures for reviewing the silicide bridging between the poly-gate and substrate region that encountered in the wafer fabrication are demonstrated. Mechanical parallel lapping, chemical de-processing, passive voltage contrast (PVC) technique using focus ion beam (FIB) or scanning electron microscope (SEM), and transmission electron microscopy (TEM) were employed for the physical analysis. View full abstract»

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  • Application of breakthrough failure analysis techniques on 90nm devices with an EOS fail

    Publication Year: 2005 , Page(s): 56 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (541 KB) |  | HTML iconHTML  

    In this investigation, a combination of old and new FA techniques has been utilized in the analysis of EOS failure in 90nm devices. We illustrate how information from conventional techniques and new innovative techniques can lead to successful root cause analysis of the failure mechanism. One of the innovative techniques used in the study is spectral analysis using infrared emission microscope (REM). It is believed that failure mechanism such as gate oxide breakdown, hot carrier effects, leaky junctions, CMOS latch-up or other leakage failures have their own unique spectrum which can be used for "defect finger-printing" analysis as presented in H. Ishizuka et al. (1990), L. WB et al. (2003), M. Rasras et al. (1997) and M. Bailon et al. (2004). It is for this purpose that spectral analysis was used during the characterization of failure mechanism in this study. Other techniques utilized were circuit simulation and frontside and backside FA techniques to physically expose the defect in the failing region. View full abstract»

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  • RFCMOS ESD protection and reliability

    Publication Year: 2005 , Page(s): 59 - 66
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the fabrication of the LNA. The measurement procedures used for the evaluation of stand-alone devices and LNAs are described. The ESD performance of standard ESD protection devices is reviewed and presents results and discussions on the ESD reliability of various ESD protection methods employed from the device point of view, followed by an outlook on the future RF ESD challenges, and conclusions. View full abstract»

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  • ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications

    Publication Year: 2005 , Page(s): 67 - 70
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    An ESD protection structure of HVPSCR embedded into the high-voltage PMOS device is proposed to greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional N+ diffusion into the drain region of HVPMOS, the It2 of output cell has been greatly improved form 0.07A to be greater than 6A within the almost same layout area. Such an ESD-enhanced VFD driver IC has been in mass production for automotive applications in car to sustain HBM ESD stress of up to 8kV. View full abstract»

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  • RC-triggered PNP and NPN simultaneously switched silicon controlled rectifier ESD networks for sub-0.18μm technology

    Publication Year: 2005 , Page(s): 71 - 75
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (330 KB) |  | HTML iconHTML  

    Silicon controlled rectifiers (SCRs) have superior ESD performance and are expected to play a major role in sub-μm technologies replacing MOSFET-based ESD networks due to MOSFET dielectric scaling. In this paper, novel polysilicon-bound SCR-based clamp circuit is explored that provide simultaneous triggering of NPN and PNP bipolar transistors by means of RC discriminator network and a triggering circuit stages coupled into the regenerative feedback loop of the SCR. This network demonstrates good ESD performance, low on-resistance, high It2 and low holding voltage. View full abstract»

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  • Use of parallel polishing technique for root cause determination of EOS devices

    Publication Year: 2005 , Page(s): 76 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3336 KB) |  | HTML iconHTML  

    In this paper, a method to investigate the root cause beyond the burnt mark using a parallel polishing technique & electrical simulation is presented with case studies. It illustrated the usefulness in analyzing the failure root cause beyond the sighting of EOS burnt marks. View full abstract»

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  • Electromigration-induced copper interconnect degradation and failure: the role of microstructure

    Publication Year: 2005 , Page(s): 85 - 91
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    In this paper, EM-induced degradation processes and failure in on-chip interconnects are discussed based on experimental studies. In-situ microscopy studies at embedded via/line dual inlaid copper interconnect test structures show that void formation and evolution depend on both interface bonding and microstructure. In future, copper microstructure becomes more critical for interconnect reliability since grain boundary diffusion becomes increasingly important for structures with strengthened interfaces, i. e. interfaces are the fastest pathways for the EM-induced mass transport any more. Particularly, grain boundaries have to be considered as significant pathways for mass transport in copper interconnects. View full abstract»

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  • Stress migration lifetime for Cu interconnects with CoWP-only cap

    Publication Year: 2005 , Page(s): 92 - 95
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    Stress migration lifetime is characterized for a CoWP-only cap process (i.e. no dielectric cap) and a CoWP + SiN cap process. For the CoWP-only process, the stress migration lifetime depends on the CoWP thickness. In order to achieve a long stress migration lifetime, the CoWP must be sufficiently thick to protect the Cu during the via etch and strip processes. The data suggests that CoWP removal is enhanced beneath partially landed vias, resulting in reduced stress migration lifetime. View full abstract»

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  • Interfacial stress characterization for stress-induced voiding in Cu/low-k interconnects

    Publication Year: 2005 , Page(s): 96 - 99
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    Stress-induced voiding (SIV) was studied in the aspects of global and localized stress variation with the change of copper geometries. Two types of interconnect structures were adopted to evaluate resistance shift versus bake time and feature size effect in Cu/low-k systems. A 3D modeling of finite element analysis (FEA) was conducted to profile the stress contour, which directly attributed to the copper voiding underneath via as well as inside via. View full abstract»

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  • Comprehensive analysis of vacancy dynamics due to electromigration

    Publication Year: 2005 , Page(s): 100 - 103
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB) |  | HTML iconHTML  

    We presented results of electromigration analysis by means of simulation for a complex interconnect structure produced by advanced process technology simulation tools. The analysis is based on a comprehensive vacancy dynamics model including all relevant driving forces accompanying electromigration. The chosen interconnect layout is resistant against electromigration failure for the applied operating conditions. View full abstract»

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  • 2D junction delineation for the failure analysis of silicon carbide devices

    Publication Year: 2005 , Page(s): 105 - 109
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (971 KB) |  | HTML iconHTML  

    In this work the 2D dopant profile of a p+n-junction as measured with SCM is compared with the potential contrast maps obtained by scanning electron microscopy (SEM). Two samples prepared by cleaving and by polishing are investigated to quantify the impact of the surface roughness on the accuracy in delineating the junction location. View full abstract»

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  • Backside deprocessing technique & its novel fault isolation application

    Publication Year: 2005 , Page(s): 110 - 113
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1129 KB) |  | HTML iconHTML  

    As process technologies are employed below 100nm, microprocessor fault isolation has become even more challenging. In this paper, we present a backside deprocessing methodology which extends fault isolation capability for silicon-on-insulator (SOI) based product. Die level failure analysis case studies using this novel methodology are demonstrated which greatly increase the fail site isolation/defect detection sensitivity with minimum failure analysis turn around time. View full abstract»

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  • Low cost etchant for Ta-based copper barrier

    Publication Year: 2005 , Page(s): 114 - 117
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    In this paper, the result of the evaluation performed on possible etchants for Ta-based Cu barrier, ammonium hydroxide (NH4OH) + hydrogen peroxide (H2O2) and potassium hydroxide (KOH) + hydrogen peroxide solutions (H2O2) and their appropriate concentration/combination is presented with recommended etching parameters. View full abstract»

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