17th IEEE Symposium on Computer Arithmetic (ARITH'05)

27-29 June 2005

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  • 17th IEEE Symposium on Computer Arithmetic - Cover

    Publication Year: 2005, Page(s): c1
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  • Proceedings. 17th IEEE Symposium on Computer Arithmetic

    Publication Year: 2005
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  • 17th IEEE Symposium on Computer Arithmetic - Copyright Page

    Publication Year: 2005, Page(s): iv
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  • 17th IEEE Symposium on Computer Arithmetic - Table of contents

    Publication Year: 2005, Page(s):v - vii
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  • Forword

    Publication Year: 2005, Page(s): viii
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  • Dedication - W. Kahan

    Publication Year: 2005, Page(s): ix
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  • Steering Committee

    Publication Year: 2005, Page(s): x
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  • Symposium Committee

    Publication Year: 2005, Page(s): xi
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  • List of referees

    Publication Year: 2005, Page(s): xii
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  • Data dependent power use in multipliers

    Publication Year: 2005, Page(s):4 - 12
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    Recent research has demonstrated the vulnerability of certain smart card architectures to power and electromagnetic analysis when multiplier operations are insufficiently shielded from external monitoring. In this paper several standard multipliers are investigated in more detail in order to provide the foundation for understanding potential weaknesses and enabling the subsequent successful repair... View full abstract»

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  • Correctly rounded multiplication by arbitrary precision constants

    Publication Year: 2005, Page(s):13 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    We introduce an algorithm for multiplying a floating-point number x by a constant C that is not exactly representable in floating-point arithmetic. Our algorithm uses a multiplication and a fused multiply and add instruction. We give methods for checking whether, for a given value of C and a given floating-point format, our algorithm returns a correctly rounded result for any x. When it does not, ... View full abstract»

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  • Decimal multiplication with efficient partial product generation

    Publication Year: 2005, Page(s):21 - 28
    Cited by:  Papers (40)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a novel design for fixed-point decimal multiplication that utilizes a simple recoding scheme to produce signed-magnitude representations of the operands thereby greatly simplifying the process of generating p... View full abstract»

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  • Long number bit-serial squarers

    Publication Year: 2005, Page(s):29 - 36
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1512 KB) | HTML iconHTML

    New bit serial squarers for long numbers in LSB first form, are presented in this paper. The first presented scheme is a 50% operational efficient squarer than has the half number of cells compared to the traditional squarers. The second scheme is a 100% operational efficient squarer. In this scheme, the number of the cells remain unchanged compared to other proposed schemes but the number of the ... View full abstract»

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  • Pain versus Gain in the Hardware Design of FPUs and Supercomputers

    Publication Year: 2005, Page(s): 39
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  • Floating-point fused multiply-add: reduced latency for floating-point addition

    Publication Year: 2005, Page(s):42 - 51
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    In this paper we propose an architecture for the computation of the double-precision floating-point multiply-add fused (MAF) operation A+(B×C) that permits to compute the floating-point addition with lower latency than floating-point multiplication and MAF. While previous MAF architectures compute the three operations with the same latency, the proposed architecture permits to skip the first... View full abstract»

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  • Some functions computable with a fused-mac

    Publication Year: 2005, Page(s):52 - 58
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    The fused multiply accumulate instruction (fused-mac) that is available on some current processors such as the Power PC or the Itanium eases some calculations. We give examples of some floating-point functions (such as ulp(x) or Nextafter(x, y)), or some useful tests, that are easily computable using a fused-mac. Then, we show that, with rounding to the nearest, the error of a fused-mac instructio... View full abstract»

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  • The vector floating-point unit in a synergistic processor element of a CELL processor

    Publication Year: 2005, Page(s):59 - 67
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    The floating-point unit in the synergistic processor element of the 1st generation multi-core CELL processor is described. The FPU supports 4-way SIMD single precision and integer operations and 2-way SIMD double precision operations. The design required a high-frequency, low latency, power and area efficiency with primary application to the multimedia streaming workloads, such as 3D graphics. The... View full abstract»

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  • New Results on the Distance between a Segment and Z ² . Application to the Exact Rounding

    Publication Year: 2005, Page(s):68 - 75
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    This paper presents extensions to Lefevre's algorithm that computes a lower bound on the distance between a segment and a regular grid Zopf2. This algorithm and, in particular, the extensions are useful in the search for worst cases for the exact rounding of unary elementary functions or base-conversion functions. The proof that is presented is simpler and less technical than the origin... View full abstract»

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  • Solving constraints on the invisible bits of the intermediate result for floating-point verification

    Publication Year: 2005, Page(s):76 - 83
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB) | HTML iconHTML

    Test generation for datapath floating-point verification involves targeting intricate corner cases, which can often be solved only through complex constraint solving. In the process of calculating the result, we use an intermediate result whose significand comprises a finite number of bits and a sticky bit that is 0 if and only if the intermediate result is exact. We refer to all the bits beyond t... View full abstract»

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  • Arithmetic Interactions: From Hardware to Applications

    Publication Year: 2005, Page(s): 87
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  • Parallel prefix adder design with matrix representation

    Publication Year: 2005, Page(s):90 - 98
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB) | HTML iconHTML

    The paper presents a one-shot batch process that generates a wide range of designs for a group of parallel prefix adders. The prefix adders are represented by two two-dimensional matrices and two vectors. This matrix representation makes it possible to compose two functions for gate sizing which calculate the delay and the total transistor width of the carry propagation graph of adders. After gate... View full abstract»

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  • High-radix implementation of IEEE floating-point addition

    Publication Year: 2005, Page(s):99 - 106
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    We are proposing a micro-architecture for high-performance IEEE floating-point addition that is based on a (non-redundant) high-radix representation of the floating-point operands. The main improvement of the proposed IEEE FP addition implementation is achieved by avoiding the computation of full alignment and normalization shifts which impose major delays in conventional implementations of IEEE F... View full abstract»

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  • Efficient mapping of addition recurrence algorithms in CMOS

    Publication Year: 2005, Page(s):107 - 113
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB) | HTML iconHTML

    Efficient adder design requires proper selection of a recurrence algorithm and its realization. Each of the algorithms: Weinberger's, Ling's and Doran's were analyzed for its flexibility in representation and suitability for realization in CMOS. We describe general techniques for developing efficient realizations based on CMOS technology constraints when using Ling's algorithm. From these techniqu... View full abstract»

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  • Synthesis of saturating counters using traditional and non-traditional basic counters

    Publication Year: 2005, Page(s):114 - 121
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    Saturating counters are a newly defined class of generalized parallel counters that provide the exact number of inputs which are equal to 1 only if this number is below a given threshold. Such counters are useful in, for example, self-test and repair units for embedded memories. This paper defines saturating counters for arbitrary threshold values and presents several alternatives for their implem... View full abstract»

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  • Division by constant for the ST100 DSP microprocessor

    Publication Year: 2005, Page(s):124 - 130
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Algorithms for Euclidean (i.e., integer) division by a constant operation are presented. They allow fast computation for some values of the divisor (known at compile time) or also when both quotient and modulus are required. These algorithms are based on the multiply-accumulate instruction and the 40-bit arithmetic available in DSPs such as the ST100 DSP from STMicroelectronics. The results are de... View full abstract»

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